公开(公告)号：US20230005549A1

公开(公告)日：2023-01-05

申请号：US17534210

申请日：2021-11-23

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/24 ,  G11C16/10 ,  G11C16/14

摘要： A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.

公开(公告)号：US20220383968A1

公开(公告)日：2022-12-01

申请号：US17518316

申请日：2021-11-03

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/34 ,  G11C11/56 ,  G11C16/10

摘要： A method of operating a semiconductor memory device includes a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes setting a state of a bit line connected to the selected memory cells, applying a program voltage to a word line connected to the selected memory cells, and performing a verify operation on the selected memory cells using a first pre-verify voltage, a second pre-verify voltage greater than the first pre-verify voltage, and a main verify voltage greater than the second pre-verify voltage. A first program permission cell, a second program permission cell, a third program permission cell, and a program prohibition cell are determined by performing the verify operation.

公开(公告)号：US20220270685A1

公开(公告)日：2022-08-25

申请号：US17393142

申请日：2021-08-03

申请人： SK hynix Inc.

发明人： Hee Youl LEE ,  Jeong Su LEE

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34

摘要： A semiconductor memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes a plurality of string groups respectively connected to a corresponding source select line among a plurality of source select lines. The peripheral circuit is configured to perform a program operation of storing data within the memory block. The control logic controls the program operation of the peripheral circuit. The plurality of source select lines are grouped into a plurality of source select line groups. The control logic controls the peripheral circuit to increase a voltage of a first source select line group including a source select line connected to a selected string group to a first level among the plurality of source select line groups.

公开(公告)号：US20220101921A1

公开(公告)日：2022-03-31

申请号：US17545634

申请日：2021-12-08

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/04 ,  G11C16/10

摘要： A method of operating a semiconductor device includes applying a first voltage to a first source select line coupled to first source select transistors of memory strings included in an unselected memory block, among memory blocks, floating the first source select line after the first voltage is applied thereto, applying a second voltage having a lower voltage level than the first voltage to a second source select line coupled to second source select transistors of the memory strings included in the unselected memory block, applying a precharge voltage to a common source line, and applying a program voltage to a word line coupled to selected memory cells of memory strings included in a selected memory block, among the memory blocks.

公开(公告)号：US20210082530A1

公开(公告)日：2021-03-18

申请号：US17107317

申请日：2020-11-30

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C7/14 ,  G11C16/24 ,  G11C16/08

摘要： A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes program ling the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups.

公开(公告)号：US20200160915A1

公开(公告)日：2020-05-21

申请号：US16749657

申请日：2020-01-22

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/12 ,  G11C16/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/04 ,  G11C16/10

摘要： Provided herein may be a memory device including a voltage generating circuit. The memory device may include a memory block including a channel layer formed between junctions included in a well, and a source select line, word lines, and drain select lines that are sequentially stacked on the well while enclosing the channel layer, a first voltage source configured to generate a first operating voltage to be applied to the well during a program operation or an erase operation, and a second voltage source configured to generate a second operating voltage to be applied to source lines that are coupled to the junctions during the program operation or the erase operation.

公开(公告)号：US20190295670A1

公开(公告)日：2019-09-26

申请号：US16441962

申请日：2019-06-14

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G06F3/06 ,  G11C16/24

摘要： Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.

公开(公告)号：US20190189229A1

公开(公告)日：2019-06-20

申请号：US16284897

申请日：2019-02-25

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  G06F3/06 ,  G11C16/24

CPC分类号： G11C16/3459 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3427

摘要： Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.

公开(公告)号：US20190057744A1

公开(公告)日：2019-02-21

申请号：US15926011

申请日：2018-03-20

申请人： SK hynix Inc.

发明人： Hee Youl LEE ,  Kyoung Cheol KWON ,  Dong Hun LEE ,  Min Kyu JEONG ,  Sung Yong CHUNG

IPC分类号： G11C16/14 ,  G11C16/30

摘要： The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

公开(公告)号：US20180315479A1

公开(公告)日：2018-11-01

申请号：US15824454

申请日：2017-11-28

申请人： SK hynix Inc.

发明人： Hee Youl LEE

IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/30 ,  G11C16/14 ,  G11C16/24

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  H01L27/11582

摘要： Provided herein may be a memory device including a voltage generating circuit. The memory device may include a memory block including a channel layer formed between Junctions included in a well, and a source select line, word lines, and drain select lines that are sequentially stacked on the well while enclosing the channel layer, a first voltage source configured to generate a first operating voltage to be applied to the well during a program operation or an erase operation, and a second voltage source configured to generate a second operating voltage to be applied to source lines that are coupled to the junctions during the program operation or the erase operation.