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1.发明申请公开(公告)号：US20210377483A1
公开(公告)日：2021-12-02
申请号：US16769830
申请日：2018-06-14
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Wan Jun ROH , Doo Bock LEE , Seung Hun LEE , Jae Jin LEE , Chun Seok JEONG
Abstract: In accordance with an embodiment of the present disclosure, an image synchronization device includes a light emitting source configured to emit light at intervals of a predetermined time, a sampling phase calibration circuit configured to calibrate a sampling phase of each of the first image sensor and the second image sensor on the basis of a light emitting timing of the light emitting source and a delay calibration circuit configured to generate delay information on the basis of a result of comparison between first image information transmitted from the first image sensor and second image information transmitted from the second image sensor.
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公开(公告)号：US20170186469A1
公开(公告)日：2017-06-29
申请号：US15096578
申请日：2016-04-12
Applicant: SK hynix Inc.
Inventor： Min Chang KIM , Chang Hyun KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G11C7/1039 , G11C5/025 , G11C5/04 , G11C7/065 , G11C7/1006 , G11C7/14 , G11C29/022 , G11C29/023 , G11C29/12005 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/46 , G11C29/48 , G11C29/56012 , G11C2029/5602
Abstract: A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.
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公开(公告)号：US20200279600A1
公开(公告)日：2020-09-03
申请号：US16879248
申请日：2020-05-20
Applicant: SK hynix Inc.
Inventor： Hyung Sik WON , Jae Jin LEE
IPC: G11C11/4094 , G11C11/4074 , G11C7/08 , G11C11/4091 , G11C11/4097
Abstract: A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.
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公开(公告)号：US20170169879A1
公开(公告)日：2017-06-15
申请号：US15080904
申请日：2016-03-25
Applicant: SK hynix Inc.
Inventor： YongWoo LEE , Jae Jin LEE , HoeKwon JEONG
IPC: G11C11/406 , G11C11/408 , G11C11/4093 , G11C11/4091
CPC classification number: G11C11/40611 , G11C8/12 , G11C11/40618 , G11C11/4085 , G11C11/4087 , G11C11/4091 , G11C11/4093
Abstract: A semiconductor system includes a semiconductor device. The semiconductor device executes an active operation according to a combination of command/address signals to store location information of mats selectively activated. In addition, the semiconductor device enters a refresh operation according to a combination of the command/address signals to selectively activate the mats included in a memory part according to the location information stored in the semiconductor device in response to a mat control signal.
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公开(公告)号：US20160372173A1
公开(公告)日：2016-12-22
申请号：US14882942
申请日：2015-10-14
Applicant: SK hynix Inc.
Inventor： Min Chang KIM , Chang Hyun KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G11C7/222 , G11C7/10 , G11C7/109 , G11C7/1093
Abstract: A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.
Abstract translation: 半导体器件可以包括缓冲器控制信号生成电路，输入控制信号生成电路和内部数据生成电路。 缓冲器控制信号生成电路可以被配置为产生缓冲器控制信号。 缓冲器控制信号可以与从写入命令信号的时间点经过预定部分的时间点同步地被使能。 输入控制信号生成电路可以被配置为响应于缓冲器控制信号而接收数据选通信号以产生输入控制信号。 内部数据产生电路可以被配置为接收数据信号以产生内部数据。
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Patent Agency Ranking
公开(公告)号：US20190206482A1
公开(公告)日：2019-07-04
申请号：US16294655
申请日：2019-03-06
Applicant: SK hynix Inc.
Inventor： Hyung Sik WON , Jae Jin LEE
IPC: G11C11/4094 , G11C11/4074 , G11C11/4091 , G11C11/4097 , G11C7/08
CPC classification number: G11C11/4094 , G11C5/147 , G11C7/08 , G11C11/404 , G11C11/4074 , G11C11/4087 , G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
Abstract: A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.
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公开(公告)号：US20180233192A1
公开(公告)日：2018-08-16
申请号：US15701754
申请日：2017-09-12
Applicant: SK hynix Inc.
Inventor： Hyung Sik WON , Jae Jin LEE
IPC: G11C11/4094 , G11C11/404 , G11C11/4074
CPC classification number: G11C11/4094 , G11C7/08 , G11C11/404 , G11C11/4074 , G11C11/4087 , G11C11/4091 , G11C11/4097 , G11C2207/002 , G11C2207/005
Abstract: A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.
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公开(公告)号：US20170256294A1
公开(公告)日：2017-09-07
申请号：US15599041
申请日：2017-05-18
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Min Chang KIM , Do Yun LEE , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G11C7/109 , G11C5/06 , G11C7/08 , G11C7/222 , G11C8/06 , G11C8/12 , G11C8/18 , G11C11/4076 , G11C11/419 , G11C29/023
Abstract: A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. The second chip may be configured to receive signals from the first chip to generate a latch address based on the received signals from the first chip.
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公开(公告)号：US20170199691A1
公开(公告)日：2017-07-13
申请号：US15162748
申请日：2016-05-24
Applicant: SK hynix Inc.
Inventor： Do Yun LEE , Min Chang KIM , Chang Hyun KIM , Jae Jin LEE , Hun Sam JUNG
CPC classification number: G06F3/0625 , G06F3/0604 , G06F3/0689 , G06F13/287
Abstract: A memory module may include a plurality of memory groups configured to include a plurality of memory packages, respectively, and input/output data through input/output pins. The memory module may include a control circuit configured to activate one or more of the plurality of memory groups on a basis of an address signal. The memory module may include a multiplexer circuit configured to couple the memory group activated on the basis of the address signal to input/output buses of the memory module.
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公开(公告)号：US20170110176A1
公开(公告)日：2017-04-20
申请号：US15058332
申请日：2016-03-02
Applicant: SK hynix Inc.
Inventor： Chang Hyun KIM , Min Chang KIM , Do Yun LEE , Yong Woo LEE , Jae Jin LEE , Hun Sam JUNG , Hoe Kwon JUNG
IPC: G11C11/406
CPC classification number: G11C11/40611 , G06F13/1636 , G11C11/40603 , G11C11/40615 , G11C11/40622 , G11C11/4087 , G11C11/4094 , G11C11/4096 , Y02D10/14
Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
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