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公开(公告)号：US12021495B2
公开(公告)日：2024-06-25
申请号：US17566334
申请日：2021-12-30
发明人： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Yan Yan , Bumkyum Kim , Aravind Kumar Padyana , Joshua Haeseok Cho , Rimal Deep Singh , Bipul Agarwal
CPC分类号： H03G3/3036 , H03F3/19 , H04B1/40 , H03F2200/451 , H03G2201/103 , H03G2201/307
摘要： Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.
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公开(公告)号：US11563460B2
公开(公告)日：2023-01-24
申请号：US17069745
申请日：2020-10-13
发明人： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
摘要： Described herein are methods for amplifying radio-frequency signals using a variable-gain amplifier with a plurality of input nodes. The methods provide a plurality of gain modes with a low gain mode or bypass mode that follows a bypass path through the variable-gain amplifier and a plurality of higher gain modes that take advantage of tailored impedances for particular gain modes. The tailored impedances can be configured to improve linearity of the amplification process in targeted gain modes. The methods can selectively couple the bypass path to a reference potential node in the plurality of higher gain modes and can selectively decouple the input nodes from a degeneration switching block in the bypass mode.
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公开(公告)号：US20220255520A1
公开(公告)日：2022-08-11
申请号：US17566334
申请日：2021-12-30
发明人： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Yan Yan , Bumkyum Kim , Aravind Kumar Padyana , Joshua Haeseok Cho , Rimal Deep Singh , Bipul Agarwal
摘要： Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.
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公开(公告)号：US20200052652A1
公开(公告)日：2020-02-13
申请号：US16546261
申请日：2019-08-20
发明人： Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
IPC分类号： H03F1/02 , H03F3/19 , H03F1/56 , H03G3/30 , H03F1/22 , H03F1/32 , H03F3/193 , H03F3/72 , H03G1/00 , H03G5/28
摘要： Disclosed herein are signal amplifiers having a plurality of amplifier cores. Individual amplifier cores can be designed for particular gain modes to enhance particular advantages while reducing other disadvantages. The signal amplifier can then switch between amplifier cores when switching gain modes to achieve desired performance characteristics (e.g., improving noise figure or linearity). Examples of signal amplifiers disclosed herein include amplifier architectures with a high gain amplifier core that reduces the noise figure and a linearity boost amplifier core that increases linearity (e.g., for lower gain modes). The disclosed signal amplifiers have a first active core with amplification chains for each of a plurality of inputs and a second active core with a single amplification chain to amplify signals received at the plurality of inputs.
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公开(公告)号：US10530412B2
公开(公告)日：2020-01-07
申请号：US16351446
申请日：2019-03-12
发明人： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
摘要： Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality. The degeneration block can be selectively isolated from a reference potential node to improve performance.
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公开(公告)号：US20180062690A1
公开(公告)日：2018-03-01
申请号：US15690947
申请日：2017-08-30
发明人： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
CPC分类号： H04B1/40 , H04B7/0882
摘要： Described herein are variable gain amplifiers that selectively provide variable or tailored impedances at a degeneration block and/or feedback block depending at least in part on a gain mode of the variable gain amplifier. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.
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公开(公告)号：US09893752B2
公开(公告)日：2018-02-13
申请号：US14727739
申请日：2015-06-01
CPC分类号： H04B1/18 , H03F3/19 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2203/7209 , H04B1/0057 , H04B7/04 , H04B7/0825
摘要： Diversity receiver front end system with variable-gain amplifiers. A receiving system can include a controller configured to selectively activate one or more of a plurality of paths between an input of a first multiplexer and an output of a second multiplexer. The receiving system can further include a plurality of bandpass filters, each one of the plurality of bandpass filters disposed along a corresponding one of the plurality of paths and configured to filter a signal received at the bandpass filter to a respective frequency band. The receiving system can further include a plurality of variable-gain amplifiers (VGAs), each one of the plurality of VGAs disposed along a corresponding one of the plurality of paths and configured to amplify a signal received at the VGA with a gain controlled by an amplifier control signal received from the controller.
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公开(公告)号：US09847804B2
公开(公告)日：2017-12-19
申请号：US14678390
申请日：2015-04-03
发明人： Junhyung Lee , Bipul Agarwal , Yong Hee Lee , Junwon Heo
摘要： Aspects of this disclosure relate to reducing insertion loss associated with a bypass path. In an embodiment, an apparatus includes a first switch having at least two throws, a second switch having at least two throws, a bypass path between the first switch and the second switch, and at least one inductor. The at least one inductor is configured to compensate for capacitance associated with the bypass path to cause insertion loss of the bypass path to be reduced.
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公开(公告)号：US09787305B2
公开(公告)日：2017-10-10
申请号：US15377820
申请日：2016-12-13
发明人： Wei Liu , Bipul Agarwal , Richard Mark Puente
IPC分类号： H04W88/08 , H03K17/74 , G05F3/08 , H01L25/16 , H01L23/495 , H01L23/373 , H01L29/868 , H01L23/66 , H02M3/07 , H01L23/00
CPC分类号： H03K17/74 , G05F3/08 , H01L23/3731 , H01L23/49503 , H01L23/49506 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L23/49589 , H01L23/49827 , H01L23/66 , H01L24/48 , H01L24/49 , H01L25/16 , H01L29/868 , H01L2223/6677 , H01L2224/05554 , H01L2224/48091 , H01L2224/48106 , H01L2224/4813 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49111 , H01L2224/49113 , H01L2924/00014 , H01L2924/00015 , H01L2924/12031 , H01L2924/1306 , H01L2924/1426 , H01L2924/15184 , H01L2924/181 , H01L2924/3011 , H02M3/07 , H03K17/693 , H03K17/76 , H04W88/08 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2924/00
摘要： Apparatus and methods for PIN diode switches for radio frequency electronic systems are provided herein. In certain configurations, a packaged switch including a packaging substrate including a die paddle and a thermally conductive substrate attached to the die paddle, one or more PIN diode switches attached to the thermally conductive substrate, and a driver chip attached to the die paddle and configured to generate a plurality of bias voltages operable to control biasing of the one or more PIN diode switches. The driver chip includes a switching regulator configured to generate a first bias voltage of the plurality of bias voltages and a charge pump configured to generate a second bias voltage of the plurality of bias voltages.
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公开(公告)号：US09628121B2
公开(公告)日：2017-04-18
申请号：US15197302
申请日：2016-06-29
IPC分类号： H04B1/04 , H04W52/02 , H04B1/3827
CPC分类号： H04B1/0475 , H03F3/24 , H03H11/1291 , H03H2011/0494 , H04B1/3833 , H04B2001/0408 , H04W52/0261 , Y02D70/00 , Y02D70/1222 , Y02D70/40
摘要： A programmable-current transmit continuous-time filter (TX-CTF) system can be included in a radio frequency (RF) transmitter. The input of the TX-CTF can receive a baseband transmission signal, and the output of the TX-CTF can be provided to an upconversion mixer for conversion to RF for transmission. The TX-CTF includes amplifier circuitry and passive circuitry that together define the filter parameters. The TX-CTF further includes programmable current circuitry that provides a programmable bias current to the amplifier circuitry. The TX-CTF system also includes control logic that receives one or more transmitter control signals and, in response, generates signals that control the bias current provided to the TX-CTF.
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