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    SEMICONDUCTOR STORAGE DEVICE
    1.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20210005618A1

    公开(公告)日：2021-01-07

    申请号：US17025191

    申请日：2020-09-18

    Applicant: SOCIONEXT INC.

    Inventor： Tomoyuki Yamada

    IPC: H01L27/112

    Abstract: A nonvolatile memory cell using vertical nanowire (VNW) FETs includes a program element of which a gate is connected to a word line, and a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line. The program element and the switch element are each constituted by one or a plurality of VNW FETs, and these VNW FETs are arranged in a line in a first direction.

    Adjustment method of signal level in semiconductor device and semiconductor device
    2.
    发明授权
    Adjustment method of signal level in semiconductor device and semiconductor device 有权
    半导体器件和半导体器件中信号电平的调整方法

    公开(公告)号：US09548090B2

    公开(公告)日：2017-01-17

    申请号：US14984779

    申请日：2015-12-30

    Applicant: Socionext Inc.

    Inventor： Morimi Arita ,  Tomoya Tsuruta ,  Tomoyuki Yamada

    IPC: G11C5/14 ,  G11C7/22

    CPC classification number: G11C7/222 ,  G11C5/148 ,  G11C8/08 ,  G11C11/418 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/5002

    Abstract: Characteristics of each transistor in a semiconductor device including a transistor of a memory cell are measured by an ASV monitoring circuit, a power supply voltage supplied to the semiconductor device is determined based on the measured characteristics of the transistor, a data read-out speed of the memory cell under the determined power supply voltage supplied is measured while changing a signal level of a word line by an SRAM word line monitoring circuit, the signal level of the word line is determined by comparing the measured data read-out speed of the memory cell and a specification range of the memory cell, and the signal level of the word line is appropriately set at the power supply voltage applied by the ASV.

    Abstract translation: 通过ASV监视电路来测量包括存储单元的晶体管的半导体器件中的每个晶体管的特性，基于所测量的晶体管的特性来确定提供给半导体器件的电源电压，数据读出速度 在通过SRAM字线监视电路改变字线的信号电平的同时测量所提供的所确定的电源电压下的存储单元，通过比较存储器的测量数据读出速度来确定字线的信号电平 单元和存储单元的规格范围，并且在由ASV施加的电源电压下适当地设置字线的信号电平。

    ADJUSTMENT METHOD OF SIGNAL LEVEL IN SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    6.
    发明申请
    ADJUSTMENT METHOD OF SIGNAL LEVEL IN SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
    半导体器件和半导体器件中信号电平的调整方法

    公开(公告)号：US20160225421A1

    公开(公告)日：2016-08-04

    申请号：US14984779

    申请日：2015-12-30

    Applicant: Socionext Inc.

    Inventor： Morimi Arita ,  Tomoya Tsuruta ,  Tomoyuki Yamada

    IPC: G11C7/22 ,  G11C5/14

    CPC classification number: G11C7/222 ,  G11C5/148 ,  G11C8/08 ,  G11C11/418 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/1202 ,  G11C2029/5002

    Abstract: Characteristics of each transistor in a semiconductor device including a transistor of a memory cell are measured by an ASV monitoring circuit, a power supply voltage supplied to the semiconductor device is determined based on the measured characteristics of the transistor, a data read-out speed of the memory cell under the determined power supply voltage supplied is measured while changing a signal level of a word line by an SRAM word line monitoring circuit, the signal level of the word line is determined by comparing the measured data read-out speed of the memory cell and a specification range of the memory cell, and the signal level of the word line is appropriately set at the power supply voltage applied by the ASV.

    Abstract translation: 通过ASV监视电路来测量包括存储单元的晶体管的半导体器件中的每个晶体管的特性，基于所测量的晶体管的特性来确定提供给半导体器件的电源电压，数据读出速度 在通过SRAM字线监视电路改变字线的信号电平的同时测量所提供的所确定的电源电压下的存储单元，通过比较存储器的测量数据读出速度来确定字线的信号电平 单元和存储单元的规格范围，并且在由ASV施加的电源电压下适当地设置字线的信号电平。

    Semiconductor device and control method thereof
    7.
    发明授权
    Semiconductor device and control method thereof 有权
    半导体装置及其控制方法

    公开(公告)号：US09390810B2

    公开(公告)日：2016-07-12

    申请号：US14852102

    申请日：2015-09-11

    Applicant: SOCIONEXT INC.

    Inventor： Tomoyuki Yamada

    IPC: G11C17/16 ,  G11C17/08 ,  G11C17/18

    CPC classification number: G11C17/08 ,  G11C17/18

    Abstract: In an OTP memory storing a one-bit of the data by two gate insulating film destruction type nonvolatile memory cells where a same bit line is connected and different word lines are connected, writings and readings of the data for selected two nonvolatile memory cells constituting one-bit are performed by simultaneously selecting the selected two nonvolatile memory cells, and verifications for the selected two nonvolatile memory cells are performed by individually selecting one and the other of the selected two nonvolatile memory cells one by one.

    Abstract translation: 在通过两个栅极绝缘膜破坏型非易失存储单元存储一位数据的OTP存储器中，其中连接相同的位线和连接不同的字线，构成一个选定的两个非易失性存储单元的数据的写入和读数 通过同时选择所选择的两个非易失性存储单元来执行位，并且通过逐个地选择所选择的两个非易失性存储单元中的一个和另一个来执行所选择的两个非易失性存储单元的验证。

    Semiconductor storage device
    9.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US11688480B2

    公开(公告)日：2023-06-27

    申请号：US17560980

    申请日：2021-12-23

    Applicant: Socionext Inc.

    Inventor： Tomoyuki Yamada

    IPC: G11C17/12 ,  H10B20/00

    CPC classification number: G11C17/12 ,  H10B20/65

    Abstract: A layout structure of a small-area one time programmable (OTP) memory using a complementary FET (CFET) is provided. The OTP memory has transistors TP as a program element and transistors TS as a switch element. The transistors TP are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The transistors TS are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The OTP memory of two bits is implemented in a small area.

    Semiconductor storage device
    10.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US11309320B2

    公开(公告)日：2022-04-19

    申请号：US17025191

    申请日：2020-09-18

    Applicant: SOCIONEXT INC.

    Inventor： Tomoyuki Yamada

    IPC: H01L27/112 ,  H01L23/522 ,  H01L23/528

    Abstract: A nonvolatile memory cell using vertical nanowire (VNW) FETs includes a program element of which a gate is connected to a word line, and a switch element that is provided between the program element and a bit line and of which a gate is connected to the word line. The program element and the switch element are each constituted by one or a plurality of VNW FETs, and these VNW FETs are arranged in a line in a first direction.

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