公开(公告)号：US09012919B2

公开(公告)日：2015-04-21

申请号：US13738406

申请日：2013-01-10

Applicant: SOITEC

Inventor： Ed Lindow ,  Chantal Arena ,  Ronald Bertram ,  Ranjan Datta ,  Subhash Mahajan

IPC: H01L29/20 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L21/0237 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/0262

Abstract: Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.

Abstract translation: 本发明的实施例涉及制造半导体结构的方法以及通过这些方法制造的半导体结构。 在一些实施例中，该方法可用于制造诸如InGaN的III-V材料的半导体结构。 通过使用不同的生长条件生长子层来制造半导体层，以改善所得层的均匀性，改善所得层的表面粗糙度和/或使层能够生长到增加的厚度而不发生 的应变松弛。