公开(公告)号：US09481944B2

公开(公告)日：2016-11-01

申请号：US13828585

申请日：2013-03-14

Applicant: SOITEC

Inventor： Chantal Arena ,  Ronald Thomas Bertram, Jr. ,  Ed Lindow ,  Christiaan Werkhoven

IPC: C30B25/14 ,  C30B25/10 ,  C30B29/40

CPC classification number: C30B25/14 ,  C30B25/10 ,  C30B29/40

Abstract: The present invention provides improved gas injectors for use with CVD (chemical vapor deposition) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high-volume manufacturing of GaN substrates.

Abstract translation: 本发明提供了用于CVD（化学气相沉积）系统的改进的气体注入器，其在注入CVD腔室之前对气体进行热化。 所提供的喷射器构造成通过加热区增加气流时间，并且包括延长加热区中的气体驻留时间的导气导管。 所提供的注射器还具有尺寸，形状和布置成以选定的流动模式注入气体的出口端口。 本发明还提供了使用所提供的热化气体喷射器的CVD系统。 本发明特别适用于高容量制造GaN衬底。

公开(公告)号：US09397258B2

公开(公告)日：2016-07-19

申请号：US14814044

申请日：2015-07-30

Applicant: Soitec

Inventor： Chantal Arena ,  Jean-Philippe Debray ,  Richard Scott Kern

IPC: H01L31/0328 ,  H01L27/15 ,  H01L21/00 ,  H01L33/06 ,  H01L33/18 ,  H01L33/00 ,  H01L33/08 ,  H01L33/12 ,  H01L33/32 ,  H01L33/14 ,  H01L21/02

CPC classification number: H01L33/06 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/0062 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/08 ,  H01L33/12 ,  H01L33/145 ,  H01L33/18 ,  H01L33/32 ,  H01L33/325 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer, and at least one barrier layer proximate the at least one well layer. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract translation: 半导体结构包括多层InGaN之间的有源区。 有源区可以至少基本上由InGaN组成。 多层InGaN包括至少一个阱层以及至少一个靠近至少一个阱层的势垒层。 形成半导体结构的方法包括生长这样的InGaN层以形成诸如LED的发光器件的有源区。 照明装置包括这样的LED。

公开(公告)号：US09337377B2

公开(公告)日：2016-05-10

申请号：US13720524

申请日：2012-12-19

Applicant: Soitec

Inventor： Chantal Arena ,  Robin Scott ,  Claudio Canizares

IPC: C30B25/16 ,  H01L31/18 ,  H01L21/36 ,  H01L33/00 ,  H01L21/02 ,  H01L27/15 ,  H01L33/32 ,  H01L33/08

CPC classification number: H01L31/184 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/0262 ,  H01L27/153 ,  H01L33/0062 ,  H01L33/0066 ,  H01L33/08 ,  H01L33/32

Abstract: Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.

Abstract translation: 原子层沉积（ALD）或ALD样沉积工艺用于制造稀氮化物III-V半导体材料。 可以使工艺气体的第一组合物流入沉积室，并且除了氮和一个或多个III族元素之外的第V族元素可以被吸附在衬底上（原子或分子形式）。 之后，可以使工艺气体的第二组合物流入沉积室，并且可以在沉积室中将N和一个或多个III族元素吸附在衬底上。 稀释氮化物III-V半导体材料的外延层可以从沉积室中的顺序吸附元件形成在衬底上。

公开(公告)号：US20160126410A1

公开(公告)日：2016-05-05

申请号：US14991100

申请日：2016-01-08

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen ,  Ding Ding ,  Li Huang

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/14 ,  H01L33/00 ,  H01L33/12

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/04 ,  H01L33/12 ,  H01L33/145 ,  H01L33/16 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract translation: 半导体结构包括多层InGaN之间的有源区。 有源区可以至少基本上由InGaN组成。 多层InGaN包括至少一个包含InwGa1-wN的阱层和至少一个包含接近至少一个阱层的InbGa1-bN的势垒层。 在一些实施例中，阱层的InwGa1-wN中的w的值在一些实施例中可以大于或等于约0.10且小于或等于约0.40，并且在InbGa1-bN中的b的值在 至少一个阻挡层可以大于或等于约0.01且小于或等于约0.10。 形成半导体结构的方法包括生长这样的InGaN层以形成诸如LED的发光器件的有源区。 照明装置包括这样的LED。

公开(公告)号：US20150380592A1

公开(公告)日：2015-12-31

申请号：US14749334

申请日：2015-06-24

Applicant: Soitec

Inventor： Fred Newman ,  Frank Reinhardt ,  Chantal Arena

IPC: H01L31/0687 ,  H01L31/18 ,  H01L31/0693

CPC classification number: H01L31/0687 ,  H01L31/03042 ,  H01L31/03046 ,  H01L31/03048 ,  H01L31/043 ,  H01L31/0693 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1852 ,  H01L31/1892 ,  Y02E10/544

Abstract: A method of fabricating a semiconductor structure includes the formation of a first bonding layer at least substantially comprised of a first III-V material on major a surface of a first element, and formation of a second bonding layer at least substantially comprised of a second III-V material on a major surface of a second element. The first bonding layer and the second bonding layer are disposed between the first element and the second element, and the first element and the second element are attached to one another at a bonding interface disposed between the first bonding layer and the second bonding layer. Semiconductor structures are fabricated using such methods.

Abstract translation: 制造半导体结构的方法包括在第一元件的主表面上形成至少基本上由第一III-V材料构成的第一结合层，以及形成至少基本上由第二III -V材料在第二元件的主表面上。 第一接合层和第二接合层设置在第一元件和第二元件之间，并且第一元件和第二元件在设置在第一接合层和第二接合层之间的接合界面处彼此附接。 使用这种方法制造半导体结构。

公开(公告)号：US20140306320A1

公开(公告)日：2014-10-16

申请号：US14314804

申请日：2014-06-25

Applicant: Soitec

Inventor： Chantal Arena

IPC: H01L29/20

CPC classification number: H01L29/2003 ,  H01L21/187 ,  H01L21/76254 ,  H01L33/0079

Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

Abstract translation: 制造半导体器件或结构的方法包括在一温度下将半导体材料层粘合到另一种材料上，随后改变半导体材料层的温度。 可以选择另一种材料以显示出热膨胀系数，使得随着半导体材料层的温度改变，控制和/或选择的晶格参数被赋予或保留在半导体材料层中。 在一些实施例中，半导体材料层可以包括III-V型半导体材料，例如氮化铟镓。 在这种方法中形成了新的中间结构。 工程衬底包括在室温下具有平均晶格参数的半导体材料层，其接近先前在升高的温度下达到的半导体材料层的平均晶格参数。

公开(公告)号：US09343626B2

公开(公告)日：2016-05-17

申请号：US14211844

申请日：2014-03-14

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen

IPC: H01L33/00 ,  H01L33/32 ,  H01L33/06 ,  H01L21/02

CPC classification number: H01L33/06 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L33/007 ,  H01L33/12 ,  H01L33/145 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

公开(公告)号：US09202741B2

公开(公告)日：2015-12-01

申请号：US13848201

申请日：2013-03-21

Applicant: Soitec

Inventor： Christiaan J. Werkhoven ,  Chantal Arena

IPC: H01L29/15 ,  H01L21/762 ,  H01L21/18 ,  H01L29/02 ,  H01L33/00 ,  H01L33/40

CPC classification number: H01L21/76256 ,  H01L21/187 ,  H01L29/02 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/40 ,  H01L2933/0016

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer and the metallic layer.

Abstract translation: 实施例涉及半导体结构及其形成方法。 在一些实施例中，所述方法可用于通过在预定深度处在供体结构中形成弱化区以制造半导体衬底，以在附着表面和弱化区之间限定转移层，以及在弱化区和弱化区之间的残留施主结构 与附接表面相对的表面。 在附着表面上形成金属层，并且在金属层和转移层之间提供欧姆接触，匹配的金属层的热膨胀系数（CTE）与转印层的CTE紧密匹配，并具有足够的刚度 为转移层提供结构支持。 在弱化区将转移层与施主结构分离，形成包含转移层和金属层的复合衬底。

公开(公告)号：US20150122313A1

公开(公告)日：2015-05-07

申请号：US14387524

申请日：2013-03-13

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Chantal Arena ,  Matteo Piccin ,  Frank Dimroth ,  Matthias Grave

IPC: H01L31/0735 ,  H01L31/18 ,  H01L31/02 ,  H01L31/047

CPC classification number: H01L31/0735 ,  C30B29/06 ,  C30B33/06 ,  H01L31/02 ,  H01L31/03046 ,  H01L31/047 ,  H01L31/0687 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1852 ,  Y02E10/544 ,  Y02P70/521

Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a first substrate with a lower surface and an upper surface; providing a second substrate with a lower surface and an upper surface; bonding the first substrate to the second substrate at the upper surface of the first substrate and the lower surface of the second substrate; and subsequently forming at least one first solar cell layer on the lower surface of the first substrate and at least one second solar cell layer at the upper surface of the second substrate.

Abstract translation: 本发明涉及一种制造多结太阳能电池器件的方法，包括以下步骤：提供具有下表面和上表面的第一基底; 提供具有下表面和上表面的第二基底; 在第一基板的上表面和第二基板的下表面处将第一基板接合到第二基板; 并且随后在所述第一基板的下表面上形成至少一个第一太阳能电池层和在所述第二基板的上表面处形成至少一个第二太阳能电池层。

公开(公告)号：US20150059832A1

公开(公告)日：2015-03-05

申请号：US14387662

申请日：2013-03-13

Applicant: Soitec

Inventor： Bruno Ghyselen ,  Chantal Arena ,  Frank Dimroth ,  Matthias Grave

IPC: H01L31/0725 ,  H01L31/0735 ,  H01L31/18

CPC classification number: H01L31/0725 ,  C30B29/06 ,  C30B33/06 ,  H01L31/03046 ,  H01L31/0687 ,  H01L31/0735 ,  H01L31/1844 ,  H01L31/1852 ,  H01L31/1892 ,  Y02E10/544 ,  Y02P70/521

Abstract: The present disclosure relates to a method for manufacturing a multi-junction solar cell device comprising the steps of: providing a final base substrate; providing a first engineered substrate comprising a first zipper layer and a first seed layer; providing a second substrate; transferring the first seed layer to the final base substrate; forming at least one first solar cell layer on the first seed layer after transferring the first seed layer to the final base substrate, thereby obtaining a first wafer structure; forming at least one second solar cell layer on the second substrate, thereby obtaining a second wafer structure; and bonding the first and the second wafer structure to each other.

Abstract translation: 本发明涉及一种用于制造多结太阳能电池器件的方法，包括以下步骤：提供最终的基底; 提供包括第一拉链层和第一种子层的第一工程衬底; 提供第二基板; 将第一种子层转移到最终的基底; 在将所述第一种子层转移到所述最终基底基板之后，在所述第一种子层上形成至少一个第一太阳能电池层，从而获得第一晶片结构; 在所述第二基板上形成至少一个第二太阳能电池层，从而获得第二晶片结构; 以及将所述第一和第二晶片结构彼此接合。