公开(公告)号：US20180124335A1

公开(公告)日：2018-05-03

申请号：US15845244

申请日：2017-12-18

Applicant: SONY CORPORATION

Inventor： Takashi MACHIDA ,  Minoru ISHIDA

IPC: H04N5/355 ,  H04N5/3745 ,  H01L27/30

CPC classification number: H04N5/355 ,  H01L27/307 ,  H04N5/35563 ,  H04N5/3745 ,  H04N5/37457 ,  H04N5/379

Abstract: A solid-state image pickup device according to the present disclosure includes: a pixel array unit, unit pixels being arranged in the pixel array unit, the unit pixels each including a plurality of photoelectric conversion sections; and a driving unit that changes a sensitivity ratio of the plurality of photoelectric conversion sections by performing intermittent driving with respect to storing of signal charges of the plurality of photoelectric conversion sections. That is, the solid-state image pickup device according to the present disclosure changes a sensitivity ratio of the plurality of photoelectric conversion sections by performing intermittent driving with respect to storing of signal charges of the plurality of photoelectric conversion sections.

公开(公告)号：US20210134861A1

公开(公告)日：2021-05-06

申请号：US17148207

申请日：2021-01-13

Applicant: SONY CORPORATION

Inventor： Harumi TANAKA ,  Yoshiaki MASUDA ,  Shinji MIYAZAWA ,  Minoru ISHIDA

IPC: H01L27/146 ,  G01N21/78 ,  G01N21/64 ,  H01L23/48 ,  H01L31/054 ,  H04N5/369 ,  H04N5/349

Abstract: The present disclosure relates to reducing the size of a solid-state imaging apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, comprising a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned, and a second structure body, comprising an output circuit unit for outputting a pixel signal. The output circuit unit, including a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.

公开(公告)号：US20200251519A1

公开(公告)日：2020-08-06

申请号：US16854565

申请日：2020-04-21

Applicant: SONY CORPORATION

Inventor： Yoshiaki MASUDA ,  Minoru ISHIDA

IPC: H01L27/146 ,  H01L21/768 ,  H04N5/369 ,  H04N5/225 ,  H01L23/532 ,  H01L23/498

Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.

公开(公告)号：US20200251511A1

公开(公告)日：2020-08-06

申请号：US16854344

申请日：2020-04-21

Applicant: SONY CORPORATION

Inventor： Harumi TANAKA ,  Yoshiaki MASUDA ,  Shinji MIYAZAWA ,  Minoru ISHIDA

IPC: H01L27/146 ,  H01L31/054 ,  H01L23/48 ,  G01N21/64 ,  G01N21/78 ,  H04N5/349

Abstract: The present disclosure relates to a solid-state imaging apparatus that can further downsize the size of the apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, at which a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned is formed, and a second structure body, at which an output circuit unit for outputting a pixel signal outputted from the pixels to the outside of the apparatus is formed. The output circuit unit, a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the pixel array unit of the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit. The present technology can be applied to, for example, solid-state imaging apparatuses and the like incorporated into wearable products and the like.

公开(公告)号：US20190103426A1

公开(公告)日：2019-04-04

申请号：US16086404

申请日：2017-03-15

Applicant: SONY CORPORATION

Inventor： Harumi TANAKA ,  Yoshiaki MASUDA ,  Shinji MIYAZAWA ,  Minoru ISHIDA

IPC: H01L27/146 ,  H04N5/349 ,  G01N21/64

Abstract: The present disclosure relates to a solid-state imaging apparatus that can further downsize the size of the apparatus. The solid-state imaging apparatus is configured by laminating a first structure body, at which a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned is formed, and a second structure body, at which an output circuit unit for outputting a pixel signal outputted from the pixels to the outside of the apparatus is formed. The output circuit unit, a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the pixel array unit of the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit. The present technology can be applied to, for example, solid-state imaging apparatuses and the like incorporated into wearable products and the like.

公开(公告)号：US20200006415A1

公开(公告)日：2020-01-02

申请号：US16564444

申请日：2019-09-09

Applicant: SONY CORPORATION

Inventor： Hiroyasu MATSUGAI ,  Hiroyuki ITOU ,  Suguru SAITO ,  Keiji OHSHIMA ,  Masanori IWASAKI ,  Toshihiko HAYASHI ,  Shuzo SATO ,  Nobutoshi FUJII ,  Hiroshi TAZAWA ,  Toshiaki SHIRAIWA ,  Minoru ISHIDA

IPC: H01L27/146 ,  B29D11/00 ,  G02B13/00

Abstract: A deformation of a stacked lens is suppressed.A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.

公开(公告)号：US20190096948A1

公开(公告)日：2019-03-28

申请号：US16085962

申请日：2017-03-13

Applicant: SONY CORPORATION

Inventor： Yoshiaki MASUDA ,  Minoru ISHIDA

IPC: H01L27/146 ,  H04N5/225 ,  H01L23/498 ,  H01L23/532

Abstract: The present disclosure relates to a semiconductor device, a solid-state image pickup element, an image pickup device, and an electronic apparatus that are enabled to reduce restrictions on materials and restrictions on device configuration. A CSP imager and a mounting substrate are connected together with a connection portion other than a solder ball. With such a configuration, restrictions on materials and restrictions on device configuration are reduced, which has conventionally occurred because it is limited to a configuration in which solder balls are used for connection. The present disclosure can be applied to image pickup devices.

公开(公告)号：US20190075261A1

公开(公告)日：2019-03-07

申请号：US15574540

申请日：2017-02-15

Applicant: SONY CORPORATION

Inventor： Takashi MACHIDA ,  Minoru ISHIDA

IPC: H04N5/355 ,  H04N5/3745

Abstract: A solid-state image pickup device according to the present disclosure includes: a pixel array unit, unit pixels being arranged in the pixel array unit, the unit pixels each including a plurality of photoelectric conversion sections; and a driving unit that changes a sensitivity ratio of the plurality of photoelectric conversion sections by performing intermittent driving with respect to storing of signal charges of the plurality of photoelectric conversion sections. That is, the solid-state image pickup device according to the present disclosure changes a sensitivity ratio of the plurality of photoelectric conversion sections by performing intermittent driving with respect to storing of signal charges of the plurality of photoelectric conversion sections.

公开(公告)号：US20180108697A1

公开(公告)日：2018-04-19

申请号：US15567289

申请日：2016-07-15

Applicant: SONY CORPORATION

Inventor： Hiroyasu MATSUGAI ,  Hiroyuki ITOU ,  Suguru SAITO ,  Keiji OHSHIMA ,  Masanori IWASAKI ,  Toshihiko HAYASHI ,  Shuzo SATO ,  Nobutoshi FUJII ,  Hiroshi TAZAWA ,  Toshiaki SHIRAIWA ,  Minoru ISHIDA

IPC: H01L27/146 ,  G02B13/00 ,  B29D11/00

CPC classification number: H01L27/14627 ,  B29D11/00375 ,  G02B1/11 ,  G02B13/0085 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687

Abstract: A deformation of a stacked lens is suppressed. A stacked lens structure has a configuration in which substrates with lenses having a lens disposed on an inner side of a through-hole formed in the substrate are bonded and stacked by direct bonding. The present technique can be applied to a camera module or the like in which a stacked lens structure in which at least three substrates with lenses including first to third substrates with lenses which are substrates with lenses in which a through-hole is formed in the substrate and a lens is formed on an inner side of the through-hole is integrated with a light receiving element, for example.

公开(公告)号：US20170317061A1

公开(公告)日：2017-11-02

申请号：US15528883

申请日：2015-12-11

Applicant: SONY CORPORATION

Inventor： Hiroshi TAKAHASHI ,  Tomofumi ARAKAWA ,  Minoru ISHIDA

IPC: H01L25/065 ,  H03K19/0175 ,  H01L25/18 ,  H01L27/146 ,  G11C5/06 ,  G11C5/02 ,  H01L23/528 ,  H01L23/48 ,  H01L21/768 ,  G11C8/10 ,  G11C7/10 ,  H04N5/907 ,  H01L27/118

Abstract: The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.