公开(公告)号：US20220376094A1

公开(公告)日：2022-11-24

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long ZHANG ,  Jie MA ,  Yan GU ,  Sen ZHANG ,  Jing ZHU ,  Jinli GONG ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

公开(公告)号：US20240072178A1

公开(公告)日：2024-02-29

申请号：US18262083

申请日：2022-03-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Hua SONG ,  Nailong HE ,  Sen ZHANG

IPC: H01L29/872 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/872 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7394 ,  H01L29/7835

Abstract: A diode and a manufacturing method therefor, and a semiconductor device. The diode includes: a substrate; an insulating buried layer provided on the substrate; a semiconductor layer provided on the insulating buried layer; anode; and a cathode, comprising: a trench-type contact, a trench being filled with a contact material, the trench extending from a first surface of the semiconductor layer to a second surface of the semiconductor layer, the first surface being a surface distant from the insulating buried layer, and the second surface being a surface facing the insulating buried layer; a cathode doped region surrounding the trench-type contact around and at the bottom of the trench-type contact, and also disposed on the first surface around the trench-type contact; and a negative electrode located on the cathode doped region and electrically connected to the cathode doped region.

公开(公告)号：US20190221560A1

公开(公告)日：2019-07-18

申请号：US16329348

申请日：2017-08-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC: H01L27/07 ,  H01L21/8234

CPC classification number: H01L27/0705 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823493 ,  H01L27/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/808

Abstract: A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.

公开(公告)号：US20240222478A1

公开(公告)日：2024-07-04

申请号：US18558422

申请日：2022-01-24

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Sen ZHANG ,  Yan GU ,  Siyu CHEN

IPC: H01L29/739 ,  H01L27/07 ,  H01L29/423 ,  H01L29/866

CPC classification number: H01L29/7394 ,  H01L27/0727 ,  H01L29/4236 ,  H01L29/866

Abstract: A reverse conducting lateral insulated-gate bipolar transistor includes a drift region formed on a substrate, a gate located on the drift region, an emitter region located on the drift region and close to one side of the gate, and a collector region located on the drift region and away from one side of the gate. Two or more N-well regions arranged at intervals are provided on the side of the drift region where the collector region is located. A P-well region is provided between the two or more N-well regions arranged at intervals; a P+ contact region is provided on the N-well region; an N+ contact region is provided on the P-well region; both the P+ contact region and the N+ contact region are conductively connected to a collector lead-out end.

公开(公告)号：US20200335607A1

公开(公告)日：2020-10-22

申请号：US16768563

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L29/06

Abstract: A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.

公开(公告)号：US20190252537A1

公开(公告)日：2019-08-15

申请号：US16329413

申请日：2017-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC: H01L29/78 ,  H01L27/098 ,  H01L29/66

CPC classification number: H01L29/7803 ,  H01L27/02 ,  H01L27/06 ,  H01L27/098 ,  H01L29/06 ,  H01L29/66712

Abstract: A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).

公开(公告)号：US20200350420A1

公开(公告)日：2020-11-05

申请号：US16957600

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265 ,  H01L21/266

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

公开(公告)号：US20200335498A1

公开(公告)日：2020-10-22

申请号：US16755817

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

IPC: H01L27/088 ,  H01L29/78

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

公开(公告)号：US20190259669A1

公开(公告)日：2019-08-22

申请号：US16329550

申请日：2017-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/808 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/45 ,  H01L21/306 ,  H01L29/40 ,  H01L27/06

Abstract: A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

公开(公告)号：US20180012980A1

公开(公告)日：2018-01-11

申请号：US15548290

申请日：2016-01-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Wei SU ,  Sen ZHANG

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/735

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).