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公开(公告)号：US11742789B2
公开(公告)日：2023-08-29
申请号：US17535176
申请日：2021-11-24
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Vanni Poletto , Paolo Vilmercati , Marco Cignoli
CPC classification number: H02P27/12 , H02P27/085
Abstract: In an embodiment, an electronic circuit includes: a controller configured to produce a pulse-width-modulated (PWM) signal to control a first current of an electrical load; a redundant current measurement circuit configured to measure the first current and provide first and second current measurement signal; a monitor circuit coupled to the redundant current measurement circuit, the monitor circuit configured to assert a current monitor signal in response to the first and second current measurement signals being found to be matching with each other, wherein the monitor circuit is configured to: detect an absence of the asserted current monitor signal prior to expiry of a threshold time interval, and in response to detecting the absence of the asserted current monitor signal, force the controller to produce, prior to expiry of the threshold time interval, a first PWM signal pulse having a controlled duty-cycle.
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公开(公告)号：US11942961B2
公开(公告)日：2024-03-26
申请号：US17713033
申请日：2022-04-04
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Oreggia , Marco Cignoli
CPC classification number: H03M1/1071 , H03M1/56 , H03M1/662 , H03M1/687
Abstract: An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.
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公开(公告)号：US11563319B1
公开(公告)日：2023-01-24
申请号：US17490285
申请日：2021-09-30
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Cignoli , Nicola Errico , Paolo Vilmercati , Stefano Castorina , Enrico Ferrara
Abstract: Disclosed herein is a single integrated circuit chip with a main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. The safety area is internally powered by an internal regulated voltage generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage while protecting against shorts of the external line delivering the external voltage. The safety area includes protection circuits that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits serving to protect against shorts of the external line delivering the external analog signals.
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Patent Agency Ranking
公开(公告)号：US11923770B2
公开(公告)日：2024-03-05
申请号：US17959797
申请日：2022-10-04
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Marco Cignoli , Vanni Poletto
Abstract: Provided is a circuit including a switching transistor having a control terminal configured to receive a control signal and having a current flow path therethrough. The switching transistor becomes conductive in response to the control signal having a first value. The current flow path through the switching transistor provides a current flow line between two nodes. In a non-conductive state, a voltage drop stress is across the switching transistor. The circuit comprises a sense transistor that is coupled to and a scaled replica of the switching transistor. The sense transistor has a sense current therethrough. The sense current is indicative of the current of the switching transistor. The circuit includes coupling circuitry configured to apply the voltage drop stress across the sense transistor in response to the switching transistor being non-conductive. In the non-conductive state, the voltage drop stress is replicated across both the switching transistor and the sense transistor.
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公开(公告)号：US20220200509A1
公开(公告)日：2022-06-23
申请号：US17535176
申请日：2021-11-24
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Vanni Poletto , Paolo Vilmercati , Marco Cignoli
Abstract: In an embodiment, an electronic circuit includes: a controller configured to produce a pulse-width-modulated (PWM) signal to control a first current of an electrical load; a redundant current measurement circuit configured to measure the first current and provide first and second current measurement signal; a monitor circuit coupled to the redundant current measurement circuit, the monitor circuit configured to assert a current monitor signal in response to the first and second current measurement signals being found to be matching with each other, wherein the monitor circuit is configured to: detect an absence of the asserted current monitor signal prior to expiry of a threshold time interval, and in response to detecting the absence of the asserted current monitor signal, force the controller to produce, prior to expiry of the threshold time interval, a first PWM signal pulse having a controlled duty-cycle.
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公开(公告)号：US11789048B2
公开(公告)日：2023-10-17
申请号：US17340559
申请日：2021-06-07
Applicant: STMicroelectronics S.r.l.
Inventor： Vanni Poletto , Nicola Errico , Paolo Vilmercati , Marco Cignoli , Vincenzo Salvatore Genna , Diego Alagna
IPC: G01R19/165 , H01H47/02 , H01H47/32
CPC classification number: G01R19/1659 , H01H47/02 , H01H47/325
Abstract: An embodiment circuit comprises high-side and low-side switches arranged between supply and reference nodes, and having an intermediate node. A switching control signal is applied with opposite polarities to the high-side and low-side switches. An inductive load is coupled between the intermediate node and one of the supply and reference nodes. Current sensing circuitry is configured to sample a first value of the load current flowing in one of the high-side and low-side switches before a commutation of the switching control signal, sample a second value of the load current flowing in the other of the high-side and low-side switches after the commutation of the switching control signal, sample a third value of the load current flowing in the other of the high-side and low-side switches after the second sampling, and generate a failure signal as a function of the first, second and third sampled values of the load current.
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公开(公告)号：US11552633B1
公开(公告)日：2023-01-10
申请号：US17502200
申请日：2021-10-15
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Cignoli
IPC: H03K17/00 , H03K17/22 , H03K19/003 , H03K17/687
Abstract: An integrated circuit (IC) includes: an input terminal; an output terminal; a first reference voltage terminal and a second reference voltage terminal; a high-side power switch coupled between the first reference voltage terminal and the output terminal; a low-side power switch coupled between the output terminal and the second reference voltage terminal; a first combinational logic and a second combination logic that are coupled to the input terminal; a first driver coupled between the first combinational logic and the high-side power switch; a second driver coupled between the second combinational logic and the low-side power switch; and first comparators coupled to the second combinational logic, where the first comparators are configured to compare a voltage difference between load path terminals of the high-side power switch with a first threshold and a second threshold.
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公开(公告)号：US20210389351A1
公开(公告)日：2021-12-16
申请号：US17340559
申请日：2021-06-07
Applicant: STMicroelectronics S.r.l.
Inventor： Vanni Poletto , Nicola Errico , Paolo Vilmercati , Marco Cignoli , Vincenzo Salvatore Genna , Diego Alagna
IPC: G01R19/165 , H01H47/32 , H01H47/02
Abstract: An embodiment circuit comprises high-side and low-side switches arranged between supply and reference nodes, and having an intermediate node. A switching control signal is applied with opposite polarities to the high-side and low-side switches. An inductive load is coupled between the intermediate node and one of the supply and reference nodes. Current sensing circuitry is configured to sample a first value of the load current flowing in one of the high-side and low-side switches before a commutation of the switching control signal, sample a second value of the load current flowing in the other of the high-side and low-side switches after the commutation of the switching control signal, sample a third value of the load current flowing in the other of the high-side and low-side switches after the second sampling, and generate a failure signal as a function of the first, second and third sampled values of the load current.
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