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公开(公告)号：US11719761B2
公开(公告)日：2023-08-08
申请号：US17407747
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
CPC classification number: G01R31/64 , G01R27/2605 , G01R31/006
Abstract: A system and method for measuring a capacitance value of a capacitor are provided. In embodiments, a resistor is coupled to a terminal of the capacitor. A difference in voltage at the terminal between a first time and a second time during a discharge routine of the capacitor is measured. The discharge routine includes sinking a current through a discharge circuit coupled to the resistor from first to second. Integration of a difference in voltage at terminals of the resistor during the discharge routine between the first and second times is also measured. The capacitance value is computed based on the measured difference in voltage, the measured integration, and the resistance value of the resistor. The health of the capacitor is determined based on a difference between the computed capacitance value and a threshold value.
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公开(公告)号：US20230054951A1
公开(公告)日：2023-02-23
申请号：US17407725
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Argento , Orazio Pennisi , Stefano Castorina , Vanni Poletto , Matteo Landini , Andrea Maino
IPC: G01R19/10 , H03M1/12 , H03M3/00 , B60R21/017
Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.
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公开(公告)号：US11079442B2
公开(公告)日：2021-08-03
申请号：US16420992
申请日：2019-05-23
Applicant: STMicroelectronics S.r.l.
Inventor： Orazio Pennisi , Valerio Bendotti , Vanni Poletto , Vittorio D'Angelo
Abstract: A method of operating a control device includes performing an open load test or a current leakage test. The open load test includes activating a first current and then a second current and sensing with the first current and the second current activated, respectively, a first voltage drop and a second voltage drop between charge distribution pins and charge sensing pins of the control device. Respective differences are calculated between the first voltage drop and the second voltage drop sensed with the first current and the second current activated, respectively. These differences are compared with respective thresholds and an open circuit condition is declared as a result of the differences calculated reaching these thresholds.
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公开(公告)号：US10560092B2
公开(公告)日：2020-02-11
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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公开(公告)号：US10215782B2
公开(公告)日：2019-02-26
申请号：US15372127
申请日：2016-12-07
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Vanni Poletto , Riccardo Miglierina , Antonio Davide Leone , Sergio Lecce
IPC: G01R19/165 , G11C27/02 , H03F3/45 , G01R31/34
Abstract: A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.
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Patent Agency Ranking
公开(公告)号：US20180175856A1
公开(公告)日：2018-06-21
申请号：US15898931
申请日：2018-02-19
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Zella , Vanni Poletto , Mauro Foppiani
IPC: H03K17/687 , G05F3/26 , H03K17/60
CPC classification number: H03K17/6872 , G05F3/26 , H03K17/60 , H03K17/687
Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.
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公开(公告)号：US20180159518A1
公开(公告)日：2018-06-07
申请号：US15634616
申请日：2017-06-27
Applicant: STMicroelectronics S.r.l.
Inventor： Vanni Poletto , Andrea Maino
IPC: H03K5/1532 , H03K7/08 , H02P27/08
CPC classification number: H03K5/1532 , H02P7/02 , H02P7/025 , H02P7/04 , H02P27/085 , H03K7/08 , H03K17/165 , H03K17/689
Abstract: A ringing peak detector module detects a ringing at the output of an inductive load driver including a bridge circuit containing high side and low side switches. A ringing peak detector receives differential feedback signals representative of the drain-source voltage of the low-side switch and detects a ringing peak of an oscillation of a current/voltage on the inductive load. A module compares said detected ringing peak with a maximum value and controls said driver by an error signal calculated as a function of the difference between said peak value and maximum value. The ringing peak detector module includes an input buffer module upstream of said peak detector circuit that shifts the differential feedback signals so a common mode of these signals is centered at a half-dynamic level of a supply voltage to provide correspondingly shifted voltages forming a shifted differential output corresponding to a steady state of the differential feedback signals.
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公开(公告)号：US12113444B2
公开(公告)日：2024-10-08
申请号：US17856657
申请日：2022-07-01
Inventor： Vanni Poletto , Antoine Pavlin
CPC classification number: H02M3/1586 , B60L53/22 , B60L58/20 , B60L2210/12 , B60L2210/14
Abstract: In an embodiment, a phase circuit includes: a bidirectional output stage configured to be coupled between a first battery and a second battery; a memory configured to store a number of active phases, and an identifier; and a synchronization circuit configured to receive a first clock signal and determine a start time of a switching cycle of the bidirectional output stage based on the number of active phases, the identifier, and the first clock signal, where the phase circuit is configured to control the timing of the switching of the bidirectional output stage based on the start time.
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公开(公告)号：US11996851B2
公开(公告)日：2024-05-28
申请号：US17556495
申请日：2021-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： Vanni Poletto , Ivan Floriani
Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.
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公开(公告)号：US20240006998A1
公开(公告)日：2024-01-04
申请号：US17856657
申请日：2022-07-01
Inventor： Vanni Poletto , Antoine Pavlin
CPC classification number: H02M3/1586 , B60L53/22 , B60L58/20 , B60L2210/12 , B60L2210/14
Abstract: In an embodiment, a phase circuit includes: a bidirectional output stage configured to be coupled between a first battery and a second battery; a memory configured to store a number of active phases, and an identifier; and a synchronization circuit configured to receive a first clock signal and determine a start time of a switching cycle of the bidirectional output stage based on the number of active phases, the identifier, and the first clock signal, where the phase circuit is configured to control the timing of the switching of the bidirectional output stage based on the start time.
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