公开(公告)号：US20170192170A1

公开(公告)日：2017-07-06

申请号：US14984563

申请日：2015-12-30

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Charles BAUDOT ,  Alain CHANTRE ,  Sébastien CREMER

IPC: G02B6/122 ,  G02B6/42 ,  G02B6/34 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B6/34 ,  G02B6/4201 ,  G02B6/4214 ,  G02B2006/12147

Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.

公开(公告)号：US20160047986A1

公开(公告)日：2016-02-18

申请号：US14804629

申请日：2015-07-21

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain CHANTRE ,  Sébastien CREMER

IPC: G02B6/136 ,  H01S5/026 ,  G02B6/42 ,  G02B6/12 ,  G02B6/132 ,  H01S5/343 ,  H01S5/02

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/132 ,  G02B6/4257 ,  G02B2006/121 ,  G02B2006/12121 ,  H01S5/0085 ,  H01S5/021 ,  H01S5/02248 ,  H01S5/026 ,  H01S5/343

Abstract: A method of manufacturing an integrated circuit including photonic components on a silicon layer and a laser made of a III-V group material includes providing the silicon layer positioned on a first insulating layer that is positioned on a support. First trenches are etched through the silicon layer and stop on the first insulating layer, and the first trenches are covered with a silicon nitride layer. Second trenches are etched through a portion of the silicon layer, and the first and second trenches are filled with silicon oxide, which are planarized. The method further includes removing the support and the first insulating layer, and bonding a wafer including a III-V group heterostructure on the rear surface of the silicon layer.

Abstract translation: 制造包括硅层上的光子分量和由III-V族材料制成的激光的集成电路的方法包括提供位于位于支撑体上的第一绝缘层上的硅层。 第一沟槽被蚀刻穿过硅层并在第一绝缘层上停止，并且第一沟槽被氮化硅层覆盖。 第二沟槽被蚀刻通过硅层的一部分，并且第一和第二沟槽用平坦化的氧化硅填充。 该方法还包括去除支撑体和第一绝缘层，以及在硅层的后表面上接合包括III-V族异质结构的晶片。

公开(公告)号：US20160233641A1

公开(公告)日：2016-08-11

申请号：US14945859

申请日：2015-11-19

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Alain CHANTRE ,  Charles BAUDOT ,  Sébastien CREMER

IPC: H01S5/026 ,  H01S5/22 ,  H01S5/125

CPC classification number: H01S5/026 ,  G02B6/12004 ,  G02B6/1225 ,  G02B6/132 ,  G02B6/136 ,  H01S5/021 ,  H01S5/0264 ,  H01S5/0265 ,  H01S5/0267 ,  H01S5/0268 ,  H01S5/0422 ,  H01S5/0425 ,  H01S5/0656 ,  H01S5/1032 ,  H01S5/1035 ,  H01S5/125 ,  H01S5/22 ,  H01S5/2206

Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.

Abstract translation: 光子集成电路包括封装至少一个金属化水平的第一绝缘区域，至少部分地封装激光源的增益介质的第二绝缘区域和放置在两个绝缘区域之间的层叠结构。 层叠结构包括第一多晶或单晶硅层，第二多晶或单晶硅层，与激光源的波长光学兼容并且可相对于硅选择性地蚀刻的中间层，并且将第一层与 所述第二层的第一部分和所述增益介质面向所述第一层的至少一部分。 第一层，中间层和第二层的第一部分形成包含谐振腔和波导的组件，光学耦合到增益介质，第二层的第二部分包含至少一个其他光子 零件。

公开(公告)号：US20170075148A1

公开(公告)日：2017-03-16

申请号：US15084645

申请日：2016-03-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Charles BAUDOT ,  Maurin DOUIX ,  Frédéric BOEUF ,  Sébastien CREMER

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F2001/0151

Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.

Abstract translation: E / O相位调制器可以包括具有绝缘衬底，单晶硅条和相同厚度的多晶硅条的波导，并且在绝缘衬底之上掺杂相反导电类型，并且在单晶之间的绝缘界面层 硅带和多晶硅条。 单晶硅带和多晶硅条中的每一个可以通过相应的延伸部横向连续，并且相应的电触点耦合到每个延伸部。