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公开(公告)号：US20170307468A1
公开(公告)日：2017-10-26
申请号：US15133614
申请日：2016-04-20
Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Jean-Francois CARPENTIER , Patrick LEMAITRE , Jean-Robert MANOUVRIER , Charles BAUDOT , Bertrand BOROT
CPC classification number: G01M11/02 , G01R31/2656 , G01R31/27 , G01R31/2884 , G01R31/303 , G01R31/311 , G01R31/31728 , G01R35/00 , G02B6/00 , G02B6/12004 , G02B6/2808 , G02B6/34
Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.
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2.发明申请公开(公告)号：US20170192170A1
公开(公告)日：2017-07-06
申请号：US14984563
申请日：2015-12-30
Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Charles BAUDOT , Alain CHANTRE , Sébastien CREMER
CPC classification number: G02B6/122 , G02B6/132 , G02B6/136 , G02B6/34 , G02B6/4201 , G02B6/4214 , G02B2006/12147
Abstract: A method is for making a photonic chip including EO devices having multiple thicknesses. The method may include forming a first semiconductor layer over a semiconductor film, forming a second semiconductor layer over the first semiconductor layer, and forming a mask layer over the second semiconductor layer. The method may include performing a first selective etching of the mask layer to provide initial alignment trenches, performing a second etching, aligned with some of the initial alignment trenches and using the first semiconductor layer as an etch stop, to provide multi-level trenches, and filling the multi-level trenches to make the EO devices having multiple thicknesses.
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3.发明申请ELECTRO-OPTIC (E/O) DEVICE WITH AN E/O AMPLITUDE MODULATOR AND ASSOCIATED METHODS 有权具有E / O振幅调制器的电光（E / O）器件及相关方法公开(公告)号：US20170059893A1
公开(公告)日：2017-03-02
申请号：US14836011
申请日：2015-08-26
Applicant: STMICROELECTRONICS (CROLLES 2) SAS , STMICROELECTRONICS SA
Inventor： Patrick LEMAITRE , Jean-Francois CARPENTIER , Charles BAUDOT , Jean-Robert MANOUVRIER
CPC classification number: G02F1/225 , G02F1/025 , G02F1/2257 , G02F2001/212 , G02F2203/15
Abstract: An electro-optic (E/O) device includes an asymmetric optical coupler having an input and first and second outputs, a first optical waveguide arm coupled to the first output of the first asymmetric optical coupler, and a second optical waveguide arm coupled to the second output of the first asymmetric optical coupler. At least one E/O amplitude modulator is coupled to at least one of the first and second optical waveguide arms. An optical combiner is coupled to the first and second optical waveguide arms downstream from the at least one E/O amplitude modulator.
Abstract translation: 电光（E / O）装置包括具有输入和第一和第二输出的不对称光耦合器，耦合到第一非对称光耦合器的第一输出的第一光波导臂和耦合到第一和第二输出的第二光波导臂 第二非对称光耦合器的第二输出。 至少一个E / O振幅调制器耦合到第一和第二光波导臂中的至少一个。 光合成器耦合到至少一个E / O振幅调制器下游的第一和第二光波导臂。
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4.发明申请公开(公告)号：US20160233641A1
公开(公告)日：2016-08-11
申请号：US14945859
申请日：2015-11-19
Applicant: STMICROELECTRONICS SA , STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Alain CHANTRE , Charles BAUDOT , Sébastien CREMER
CPC classification number: H01S5/026 , G02B6/12004 , G02B6/1225 , G02B6/132 , G02B6/136 , H01S5/021 , H01S5/0264 , H01S5/0265 , H01S5/0267 , H01S5/0268 , H01S5/0422 , H01S5/0425 , H01S5/0656 , H01S5/1032 , H01S5/1035 , H01S5/125 , H01S5/22 , H01S5/2206
Abstract: A photonic integrated circuit includes a first insulating region encapsulating at least one metallization level, a second insulating region at least partially encapsulating a gain medium of a laser source, and a stacked structure placed between the two insulating regions. The stacked structure includes a first polycrystalline or single-crystal silicon layer, a second polycrystalline or single-crystal silicon layer, an intermediate layer optically compatible with the wavelength of the laser source and selectively etchable relative to silicon and that separates the first layer from a first portion of the second layer, and the gain medium facing at least one portion of the first layer. The first layer, the intermediate layer, and the first portion of the second layer form an assembly containing a resonant cavity and a waveguide, which are optically coupled to the gain medium, and a second portion of the second layer containing at least one other photonic component.
Abstract translation: 光子集成电路包括封装至少一个金属化水平的第一绝缘区域，至少部分地封装激光源的增益介质的第二绝缘区域和放置在两个绝缘区域之间的层叠结构。 层叠结构包括第一多晶或单晶硅层，第二多晶或单晶硅层，与激光源的波长光学兼容并且可相对于硅选择性地蚀刻的中间层，并且将第一层与 所述第二层的第一部分和所述增益介质面向所述第一层的至少一部分。 第一层，中间层和第二层的第一部分形成包含谐振腔和波导的组件，光学耦合到增益介质，第二层的第二部分包含至少一个其他光子 零件。
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公开(公告)号：US20220091330A1
公开(公告)日：2022-03-24
申请号：US17540626
申请日：2021-12-02
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frederic BOEUF , Charles BAUDOT
Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
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Patent Agency Ranking
公开(公告)号：US20220013681A1
公开(公告)日：2022-01-13
申请号：US17486219
申请日：2021-09-27
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Charles BAUDOT , Sebastien CREMER , Nathalie VULLIET , Denis PELLISSIER-TANON
IPC: H01L31/109 , H01L31/18 , H01L31/0232 , H01L31/028 , H01L31/105
Abstract: A photodiode includes an active area formed by intrinsic germanium. The active area is located within a cavity formed in a silicon layer. The cavity is defined by opposed side walls which are angled relative to a direction perpendicular to a bottom surface of the silicon layer. The angled side walls support epitaxial growth of the intrinsic germanium with minimal lattice defects.
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公开(公告)号：US20210257507A1
公开(公告)日：2021-08-19
申请号：US17308651
申请日：2021-05-05
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Charles BAUDOT , Sebastien CREMER , Nathalie VULLIET , Denis PELLISSIER-TANON
IPC: H01L31/105 , H01L31/0232 , G02B6/12 , H01L31/028
Abstract: A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material.
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公开(公告)号：US20200241201A1
公开(公告)日：2020-07-30
申请号：US16847189
申请日：2020-04-13
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Frederic BOEUF , Charles BAUDOT
Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.
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公开(公告)号：US20200233164A1
公开(公告)日：2020-07-23
申请号：US16748696
申请日：2020-01-21
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Jean-Francois CARPENTIER , Charles BAUDOT
Abstract: A photonic system includes a first photonic circuit having a first face and a second photonic circuit having a second face. The first photonic circuit comprises first wave guides, and, for each first wave guide, a second wave guide covering the first wave guide, the second wave guides being in contact with the first face and placed between the first face and the second face, the first wave guides being located on the side of the first face opposite the second wave guides. The second photonic circuit comprises, for each second wave guide, a third wave guide covering the second wave guide. The first photonic circuit comprises first positioning devices projecting from the first face and the second photonic circuit comprises second positioning devices projecting from the second face, at least one of the first positioning devices abutting one of the second positioning devices in a first direction.
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公开(公告)号：US20170184797A1
公开(公告)日：2017-06-29
申请号：US14982302
申请日：2015-12-29
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Charles BAUDOT
CPC classification number: G02B6/34 , G02B5/1857 , G02B5/1866 , G02B6/124 , G02B6/30 , G02B2006/12061
Abstract: An electro-optic device may include a photonic chip including an insulator layer, and a semiconductor layer over the insulator layer and defining an optical grating coupler. The optical grating coupler may have a series of alternating curved ridges and valleys. The optical grating coupler has first and second sides and a medial portion. The medial portion has a medial grating period T based upon a targeting wavelength. One or more of the first and second sides have a side grating period different than T.
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