公开(公告)号：US20170317106A1

公开(公告)日：2017-11-02

申请号：US15361937

申请日：2016-11-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe Boivin ,  Franck Arnaud ,  Gregory Bidal ,  Dominique Golanski ,  Emmanuel Richard

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

CPC classification number: H01L27/1207 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4916

Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.

公开(公告)号：US20170069764A1

公开(公告)日：2017-03-09

申请号：US15356022

申请日：2016-11-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gregory Bidal

IPC: H01L29/786 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0684 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

Abstract translation: MOS晶体管包括搁置在绝缘体上并具有基本平坦的上表面的半导体层。 半导体层在沟道区域中向下延伸到第一深度，并且在源极和漏极区域中向下延伸大于第一深度的第二深度。 在沟道区域中，半导体层由绝缘体上硅衬底的上半导体层的一部分形成。 在源区和漏区中，通过外延生长的半导体材料形成半导体层。

公开(公告)号：US20170117296A1

公开(公告)日：2017-04-27

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

公开(公告)号：US09941416B2

公开(公告)日：2018-04-10

申请号：US15356022

申请日：2016-11-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gregory Bidal

IPC: H01L31/119 ,  H01L29/786 ,  H01L21/762 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0684 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

公开(公告)号：US09786755B2

公开(公告)日：2017-10-10

申请号：US14930150

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique Golanski ,  Gregory Bidal ,  Simon Jeannot

IPC: H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

CPC classification number: H01L29/42364 ,  H01L27/12 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7838 ,  H01L29/7881

Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

公开(公告)号：US09530686B1

公开(公告)日：2016-12-27

申请号：US15043830

申请日：2016-02-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gregory Bidal

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/28026 ,  H01L21/28158 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0684 ,  H01L29/42364 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

Abstract translation: MOS晶体管包括搁置在绝缘体上并具有基本平坦的上表面的半导体层。 半导体层在沟道区域中向下延伸到第一深度，并且在源极和漏极区域中向下延伸大于第一深度的第二深度。 在沟道区域中，半导体层由绝缘体上硅衬底的上半导体层的一部分形成。 在源区和漏区中，通过外延生长的半导体材料形成半导体层。

公开(公告)号：US09876032B2

公开(公告)日：2018-01-23

申请号：US15296205

申请日：2016-10-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Sonarith Chhun ,  Emmanuel Josse ,  Gregory Bidal ,  Dominique Golanski ,  Francois Andrieu ,  Jerome Mazurier ,  Olivier Weber

IPC: H01L21/336 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L27/1203 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/6653

Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

公开(公告)号：US20160284807A1

公开(公告)日：2016-09-29

申请号：US14930324

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Frederic Monsieur ,  Xavier Federspiel ,  Gregory Bidal

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/42364 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/127 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/7838

Abstract: A substrate of the silicon-on-insulator type is formed from an initial substrate of the silicon-on-insulator type having a semiconductor film on top of a buried insulating layer itself situated on top of a carrier substrate. A localized modification of a thickness of the semiconductor film is made so as to form a semiconductor film having different thicknesses in different regions.

Abstract translation: 绝缘体上硅型的衬底由绝缘体上硅型的初始衬底形成，其中半导体膜位于位于载体衬底顶部的掩埋绝缘层本身的顶部上。 制造半导体膜的厚度的局部修改以便形成在不同区域中具有不同厚度的半导体膜。

公开(公告)号：US20160276451A1

公开(公告)日：2016-09-22

申请号：US14930150

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique Golanski ,  Gregory Bidal ,  Simon Jeannot

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/788 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L27/12 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7838 ,  H01L29/7881

Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

Abstract translation: 集成电路包括用于第一晶体管的第一区和用于第二晶体管的第二区。 晶体管由绝缘体上的类型的衬底支撑，其中包括在载体衬底上的掩埋绝缘层上的半导体膜。 在第二区域中，已经去除了半导体膜。 第二区域中的第二晶体管包括搁置在由掩埋绝缘层的一部分形成的载体衬底上的栅极介电区域）。 第一区域中的第一晶体管包括由半导体膜上的电介质层形成的栅介电区域。

公开(公告)号：US20130099322A1

公开(公告)日：2013-04-25

申请号：US13659768

申请日：2012-10-24

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Emmanuel Perrin ,  Gregory Bidal ,  Raul Andres Bianchi

IPC: H01L29/78 ,  H01L21/283

CPC classification number: H01L21/76237 ,  H01L21/28229 ,  H01L21/823481 ,  H01L29/513 ,  H01L29/518

Abstract: A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate.

Abstract translation: 一种用于限定半导体衬底中的绝缘区域的方法，包括在衬底中限定的沟槽的壁和底部上形成接合层的步骤。 至少靠近所述半导体衬底的表面钝化所述接合层的表观表面的步骤。