-
公开(公告)号：US20240334080A1
公开(公告)日：2024-10-03
申请号：US18616454
申请日：2024-03-26
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent SIMONY
IPC: H04N25/616 , H03F3/45 , H04N25/709 , H04N25/77
CPC classification number: H04N25/616 , H03F3/45475 , H04N25/709 , H04N25/77 , H03F2200/69
Abstract: An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.
-
公开(公告)号：US20200312896A1
公开(公告)日：2020-10-01
申请号：US16829837
申请日：2020-03-25
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent SIMONY
IPC: H01L27/146 , H04N5/369
Abstract: A global shutter pixel includes a first transistor and a first switch series-connected between a first node of application of a potential and an internal node of the pixel. A control terminal of the first transistor is coupled to a floating diffusion node of the pixel. At least two assemblies are coupled to the internal node, where each assembly is formed of a capacitor series-connected with a second switch coupling the capacitor to the internal node. A second transistor has a control terminal connected to the internal node and a first conduction terminal coupled to an output node of the pixel. The pixel operation is controlled to store an initialization voltage from the floating diffusion on one of the capacitors and a pixel integration voltage from the floating diffusion on another of the capacitors.
-
Patent Agency Ranking
公开(公告)号：US20200382738A1
公开(公告)日：2020-12-03
申请号：US16890877
申请日：2020-06-02
Inventor： Pierre MALINGE , Frederic LALANNE , Laurent SIMONY
IPC: H04N5/3745
Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.
-
公开(公告)号：US20240213972A1
公开(公告)日：2024-06-27
申请号：US18541324
申请日：2023-12-15
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Laurent SIMONY
IPC: H03K5/24 , H04N25/772 , H04N25/778
CPC classification number: H03K5/2481 , H04N25/772 , H04N25/778 , H03M1/56
Abstract: A differential comparator circuit includes a voltage amplifier of negative gain receiving an analog input signal and generating an inverted analog input signal. The analog input signal and the inverted analog input signal form differential analog input signals. A comparator input circuit includes a first capacitive divider to generate a first signal as an average of the analog input signal and a first ramp signal, and a second capacitive divider to generate a second signal as an average of the inverted analog input signal and a second ramp signal, with the first and second ramp signals being differential ramp signals. The comparator is configured to compare the first and second signals to generate a signal transition having a timing based on the input signal.
-
公开(公告)号：US20160134297A1
公开(公告)日：2016-05-12
申请号：US14835980
申请日：2015-08-26
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Laurent SIMONY
IPC: H03M1/20 , H01L27/146 , H03M1/36 , H03M1/00 , H03M1/06
CPC classification number: H03M1/20 , H01L27/14643 , H03M1/002 , H03M1/0604 , H03M1/188 , H03M1/36 , H03M1/56
Abstract: A method includes a first analog/digital conversion of an analog signal over m bits, with m less than n, associated with a first full-scale value, and a second analog/digital conversion of the analog signal over m bits associated with a second full-scale value 2n-m times bigger than the first. The two analog/digital conversions are carried out simultaneously and respectively delivering a first intermediate digital word of m bits and a second intermediate digital word of m bits. The method also includes a digital post-processing carried out after the two analog/digital conversions and generating an n-bit digital word starting from at least one of the two intermediate digital words extended to n bits and from at least one threshold digital indication representative of at least one threshold lower than or equal to the first full-scale value.
Abstract translation: 一种方法包括通过m比特的模拟信号的第一模拟/数字转换，具有与第一满量程值相关联的m小于n的模拟信号，以及在与第二满量程相关联的m位上的模拟信号的第二模拟/数字转换 全尺寸值比第一大2n-m倍。 两个模拟/数字转换同时执行，分别传送m位的第一中间数字字和m位的第二中间数字字。 该方法还包括在两个模拟/数字转换之后执行的数字后处理，并产生从扩展到n位的两个中间数字字中的至少一个开始的n位数字字，以及从至少一个阈值数字指示代表 的至少一个阈值小于或等于第一满量程值。
-
公开(公告)号：US20230071932A1
公开(公告)日：2023-03-09
申请号：US17885960
申请日：2022-08-11
Inventor： Laurent SIMONY , Frederic LALANNE
IPC: H01L27/146
Abstract: An image sensor includes an array of pixels inside and on top of a substrate. A control circuit is configured to apply voltage potentials to the substrate. During a first phase, the control circuit applies a ground potential to the substrate. During a second phase, the control circuit applies a potential positive with respect to the ground potential to the substrate.
-
公开(公告)号：US20200382731A1
公开(公告)日：2020-12-03
申请号：US16890944
申请日：2020-06-02
Inventor： Laurent SIMONY , Pierre MALINGE
Abstract: A sensor includes pixels each including: a first transistor and a first switch in series between a first node and an internal node of the pixel, a gate of the first transistor being coupled to a second node; a capacitive element, a first terminal of which is connected to the second node; and a plurality of assemblies each including a capacitance in series with a second switch coupled to the internal node. The sensor includes a circuit configured to control, each time a voltage is stored in one of the assemblies, the interruption of a current between the first node and the internal node: by switching a first potential applied to a second terminal of the capacitive element; or by opening the first switch.
-
-
-
-
-
-
Search Results
7
records
(took 0.012 seconds)
