公开(公告)号：US20220320332A1

公开(公告)日：2022-10-06

申请号：US17694276

申请日：2022-03-14

Applicant: STMicroelectronics Pte Ltd

Inventor： Yean Ching YONG ,  Maurizio Gabriele CASTORINA ,  Voon Cheng NGWAN ,  Ditto ADNAN ,  Fadhillawati TAHIR ,  Churn Weng YIM

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L21/764 ,  H01L21/765 ,  H01L29/66

Abstract: An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region buried in the semiconductor substrate providing a body and a second doped region in the semiconductor substrate providing a source. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region that may have void inclusion. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region. A pair of gate contacts are provided at each trench. The pair of gate contacts includes: a first gate contact extending into the first gate lobe at a location laterally offset from the void and a second gate contact extending into the second gate lobe at a location laterally offset from the void.

公开(公告)号：US20240404905A1

公开(公告)日：2024-12-05

申请号：US18538935

申请日：2023-12-13

Applicant: STMicroelectronics Pte Ltd

Inventor： Eng Hui GOH ,  Voon Cheng NGWAN ,  Fadhillawati TAHIR ,  Ditto ADNAN ,  Boon Kiat TUNG ,  Maurizio Gabriele CASTORINA

IPC: H01L23/31 ,  H01L21/02 ,  H01L27/06

Abstract: An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

公开(公告)号：US20220189840A1

公开(公告)日：2022-06-16

申请号：US17518215

申请日：2021-11-03

Applicant: STMicroelectronics Pte Ltd

Inventor： Eng Hui GOH ,  Voon Cheng NGWAN ,  Fadhillawati TAHIR ,  Ditto ADNAN ,  Boon Kiat TUNG ,  Maurizio Gabriele CASTORINA

IPC: H01L23/31 ,  H01L29/51 ,  H01L29/45

Abstract: An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

公开(公告)号：US20230238341A1

公开(公告)日：2023-07-27

申请号：US18079610

申请日：2022-12-12

Applicant: STMicroelectronics Pte Ltd

Inventor： Churn Weng YIM ,  Maurizio Gabriele CASTORINA ,  Voon Cheng NGWAN ,  Yean Ching YONG ,  Ditto ADNAN ,  Fadhillawati TAHIR

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/022 ,  H01L2224/0219 ,  H01L2224/03019 ,  H01L2224/03466 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647

Abstract: A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.

公开(公告)号：US20220393022A1

公开(公告)日：2022-12-08

申请号：US17730895

申请日：2022-04-27

Applicant: STMicroelectronics PTE LTD ,  STMicroelectronics (Tours) SAS

Inventor： Shin Phay LEE ,  Voon Cheng NGWAN ,  Frederic LANOIS ,  Fadhillawati TAHIR ,  Ditto ADNAN

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/66

Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.