公开(公告)号：US11894328B2

公开(公告)日：2024-02-06

申请号：US17751982

申请日：2022-05-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Jung-Hsing Chien

IPC分类号： H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L24/05 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/13 ,  H01L29/41725 ,  H01L29/4236 ,  H01L2224/0217 ,  H01L2224/0219 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/03019 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05573 ,  H01L2224/10135

摘要： The present application provides a semiconductor device with an edge-protecting spacer over a bonding pad. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a dielectric liner disposed between the first spacer and the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad.

公开(公告)号：US09905522B1

公开(公告)日：2018-02-27

申请号：US15254640

申请日：2016-09-01

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yusheng Lin

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L21/304 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

CPC分类号： H01L24/05 ,  H01L21/02035 ,  H01L21/26513 ,  H01L21/304 ,  H01L21/324 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/2076 ,  H01L2924/00014

摘要： Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

公开(公告)号：US09754905B1

公开(公告)日：2017-09-05

申请号：US15292433

申请日：2016-10-13

申请人： International Business Machines Corporation

发明人： Ekta Misra ,  Krishna R. Tunga

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05191 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/05691 ,  H01L2224/05693 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0455 ,  H01L2924/01073 ,  H01L2924/04541 ,  H01L2924/0469 ,  H01L2924/0463 ,  H01L2924/01013 ,  H01L2924/0476 ,  H01L2924/01074 ,  H01L2924/0496 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2924/0479 ,  H01L2924/01027 ,  H01L2924/048 ,  H01L2924/01028 ,  H01L2924/01006

摘要： Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

公开(公告)号：US20170243840A1

公开(公告)日：2017-08-24

申请号：US15588913

申请日：2017-05-08

申请人： Renesas Electronics Corporation

发明人： Hiroaki SEKIKAWA

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05664 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00013

摘要： To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

公开(公告)号：US09543259B2

公开(公告)日：2017-01-10

申请号：US14504053

申请日：2014-10-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yung-Ping Chiang ,  Chao-Wen Shih ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L21/3105

CPC分类号： H01L24/02 ,  H01L21/31053 ,  H01L21/56 ,  H01L22/12 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/03334 ,  H01L2224/03462 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/11602 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/92 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/11

摘要： A semiconductor structure includes a semiconductive substrate, a post passivation interconnect (PPI) and a polymer layer. The PPI is disposed above the semiconductive substrate and includes a landing area for receiving a conductor. The polymer layer is on the PPI, wherein the conductor is necking a turning point so as to include an oval portion being substantially surrounded by the polymer layer, and the oval portion of the conductor is disposed on the landing area of the PPI.

摘要翻译： 半导体结构包括半导体衬底，后钝化互连（PPI）和聚合物层。 PPI设置在半导体衬底之上，并且包括用于接收导体的着陆区域。 聚合物层在PPI上，其中导体颈缩转折点，以便包括基本上被聚合物层包围的椭圆形部分，并且导体的椭圆形部分设置在PPI的着陆区域上。

公开(公告)号：US20160358882A1

公开(公告)日：2016-12-08

申请号：US15238532

申请日：2016-08-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Yin Liu ,  Lan-Lin Chao ,  Cheng-Tai Hsiao ,  Xin-Hua Huang ,  Hsun-Chung Kuang

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/80 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/89 ,  H01L25/0657 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03616 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/0516 ,  H01L2224/05546 ,  H01L2224/05547 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06517 ,  H01L2224/08147 ,  H01L2224/80011 ,  H01L2224/80012 ,  H01L2224/80013 ,  H01L2224/80014 ,  H01L2224/8084 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/8192 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001

摘要： A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.

公开(公告)号：US20160329288A1

公开(公告)日：2016-11-10

申请号：US15215037

申请日：2016-07-20

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： SHEILA F. CHOPIN ,  MIN DING ,  VARUGHESE MATHEW ,  SCOTT S. ROTH

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/03015 ,  H01L2224/03019 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

摘要翻译： 通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极 在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

公开(公告)号：US09418949B2

公开(公告)日：2016-08-16

申请号：US14028554

申请日：2013-09-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chung-Hsin Lin ,  Ping-Heng Wu ,  Chao-Wen Lay ,  Hung-Mo Wu ,  Ying-Cheng Chuang

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L23/52 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/525

CPC分类号： H01L24/05 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L23/562 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.

摘要翻译： 本发明提供一种半导体器件，其包括衬底，电介质层，虚拟焊盘，焊盘，再分配层和金属互连。 衬底包括非器件区域和器件区域。 介电层位于非器件区域和器件区域上。 虚拟焊盘位于非器件区的介质层上。 金属互连在非器件区的介质层中并连接到虚拟焊盘。 焊盘位于器件区域的介电层上。 缓冲层位于接合焊盘和电介质层之间。 缓冲层包括金属，金属氮化物或其组合。 再分布层在电介质层上并连接虚拟焊盘和焊盘。

公开(公告)号：US09385081B2

公开(公告)日：2016-07-05

申请号：US14637456

申请日：2015-03-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Chih Wang ,  Yao-Hsiang Liang

IPC分类号： H01L29/20 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L27/088 ,  H01L23/522

CPC分类号： H01L24/05 ,  H01L21/76841 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/13 ,  H01L27/088 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01031 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/13091 ,  H01L2924/206 ,  H01L2924/30201 ,  H01L2924/00 ,  H01L2924/00014

摘要： A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

公开(公告)号：US20160148883A1

公开(公告)日：2016-05-26

申请号：US15010022

申请日：2016-01-29

申请人： Texas Instruments Incorporated

发明人： Brian Zinn

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L21/76847 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/02181 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/0345 ,  H01L2224/03616 ,  H01L2224/0382 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05676 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/13055 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941

摘要： A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

摘要翻译： 形成接合焊盘的方法包括提供包括形成在其上的集成电路（IC）器件的衬底，其具有可氧化的最上面的金属互连层，其提供耦合到IC器件上的电路节点的多个接合焊盘。 多个接合焊盘包括金属焊盘区域。 至少一个钝化层提供包括金属接合焊盘区域上方的电介质侧壁的沟槽。 钌（Ru）层直接沉积在电介质侧壁上，直接沉积在金属焊盘区域上，这消除了对沟槽电介质侧壁衬垫的阻挡层的需要。 图案化Ru层以为多个接合焊盘提供接合焊盘表面。