公开(公告)号：US20040108571A1

公开(公告)日：2004-06-10

申请号：US10716249

申请日：2003-11-18

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: H01L029/00

CPC classification number: H01L27/14603 ,  H01L27/1443 ,  H01L27/14643 ,  H01L31/03529 ,  Y02E10/50

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract translation: 提供一种集成电路，其包括结合有具有p-n结的半导体光电二极管器件的衬底。 该光电二极管装置包括至少一个电容沟槽，该电容沟槽埋设在该衬底中，并与该结点并联连接。 在优选实施例中，衬底由硅形成，并且电容沟槽包括由绝缘壁部分包围的内部掺杂硅区域，该绝缘壁横向分离内部区域与衬底。 还提供了一种制造集成电路的方法，该集成电路包括具有p-n结的半导体光电二极管器件的衬底。

公开(公告)号：US20020094678A1

公开(公告)日：2002-07-18

申请号：US10044402

申请日：2002-01-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: C21D001/00

CPC classification number: H01L21/76235 ,  H01L21/02667 ,  H01L21/2022

Abstract: An initial single-crystal substrate 1 having, locally and on the surface, at least one discontinuity in the single-crystal lattice is formed. The initial substrate is recessed at the discontinuity. The single-crystal lattice is amorphized around the periphery ofthe recess. A layer ofamorphous material having the same chemical composition as that ofthe initial substrate is deposited on the structure obtained. The structure obtained is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice ofthe initial substrate.

Abstract translation: 形成了在局部和表面上形成单晶格中的至少一个不连续性的初始单晶衬底1。 初始衬底在不连续处凹进。 单晶晶格围绕凹槽的周边非晶化。 在所获得的结构上沉积具有与初始底物相同的化学组成的无定形材料层。 对所获得的结构进行热退火，以使非晶材料重结晶，从而与初始衬底的单晶晶格连续。

公开(公告)号：US20030025125A1

公开(公告)日：2003-02-06

申请号：US10142249

申请日：2002-05-09

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Herve Jaouen

IPC: H01L029/74

CPC classification number: H01L29/1012 ,  H01L29/0649 ,  H01L29/735

Abstract: The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator area 20. An intrinsic collector region is situated in the bulk separator area 20 in contact with the extrinsic collector region. An intrinsic base region 100 is formed which is thinner laterally than vertically and in contact with the intrinsic collector region and in contact with the emitter region through bearing on a vertical flank of the first isolating well facing a vertical flank of the second isolating well. An extrinsic base region 60 is formed which is substantially perpendicular to the intrinsic base region in the top part of the bulk separator area, and contact terminals C, B, E respectively in contact with the extrinsic collector region, the extrinsic base region, and the emitter region.

Abstract translation: 晶体管包括设置在半导体本体中形成的第一隔离阱11,150中的发射极区17。 非本征集电极区域16设置在形成于半导体本体SB中的第二隔离阱3,150中，并通过体分离器区域20与第一阱的横向分离。本体集电极区域位于与本体分离器区域20接触的本体分离器区域20中 外部集电极区域。 形成本征基区100，其横向比垂直地更薄并且与本征收集区相接触，并且通过轴承在第一隔离井的垂直侧面与第二隔离井的垂直侧面的垂直侧面接触。 形成基本上垂直于本体分离器区域的顶部中的本征基极区域的外部基极区域60，以及分别与外部基极区域，外部基极区域和外部基极区域接触的接触端子C，B，E 发射区。

公开(公告)号：US20030013262A1

公开(公告)日：2003-01-16

申请号：US10171102

申请日：2002-06-13

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Herve Jaouen

IPC: H01L021/331 ,  H01L021/22 ,  H01L021/38

CPC classification number: H01L29/66272

Abstract: A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a time such that a first dopant diffuses into a first zone and a second dopant diffuses into a second zone larger than the first zone.

Abstract translation: 一种制造集成电路的方法，该集成电路包括单晶硅衬底，在该衬底的顶表面上的多晶硅层，并且掺杂有至少两种具有不同扩散速率的掺杂剂，其中在温度和 时间，使得第一掺杂剂扩散到第一区域中，并且第二掺杂剂扩散到大于第一区域的第二区域中。

公开(公告)号：US20020119620A1

公开(公告)日：2002-08-29

申请号：US10044812

申请日：2002-01-11

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: H01L021/8242

CPC classification number: H01L27/10867 ,  H01L21/02667 ,  H01L21/2022 ,  H01L27/10832

Abstract: The integrated circuit comprises a semiconductor substrate SB supporting a memory cell PM of the DRAM type comprising an access transistor T and a storage capacitor TRC. The access transistor is made on the substrate, and the substrate includes a capacitive trench TRC buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.

Abstract translation: 集成电路包括支持DRAM型存储单元PM的半导体衬底SB，包括存取晶体管T和存储电容器TRC。 存取晶体管制成在衬底上，并且衬底包括埋在晶体管下面并形成存储电容器的电容沟槽TRC，电容沟槽与晶体管的源极和漏极区域之一接触。

公开(公告)号：US20020113233A1

公开(公告)日：2002-08-22

申请号：US10044286

申请日：2002-01-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: H01L031/20 ,  H01L031/036 ,  H01L029/88 ,  H01L029/04

CPC classification number: H01L27/14603 ,  H01L27/1443 ,  H01L27/14643 ,  H01L31/03529 ,  Y02E10/50

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract translation: 提供一种集成电路，其包括结合有具有p-n结的半导体光电二极管器件的衬底。 该光电二极管装置包括至少一个电容沟槽，该电容沟槽埋设在该衬底中，并与该结点并联连接。 在优选实施例中，衬底由硅形成，并且电容沟槽包括由绝缘壁部分包围的内部掺杂硅区域，该绝缘壁横向分离内部区域与衬底。 还提供了一种制造集成电路的方法，该集成电路包括具有p-n结的半导体光电二极管器件的衬底。

公开(公告)号：US20020109188A1

公开(公告)日：2002-08-15

申请号：US10044829

申请日：2002-01-11

Applicant: STMICROELECTRONICS S.A.

Inventor： Olivier Menut ,  Guillaume Bouche ,  Herve Jaouen

IPC: H01L027/01

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. The horizontal isolating layer may be a layer of constant thickness or a crenellated layer.

Abstract translation: 半导体器件包括半导体衬底（SB），其具有局部至少一个区域（ZL），该区域（ZL）终止于衬底的表面，并且沿着其侧边缘及其底部通过绝缘材料整齐地界定，从而与绝缘材料完全隔离 底物的剩余部分。 水平隔离层可以是恒定厚度的层或钝化层。