-
1.发明申请LOW VOLTAGE ISOLATION SWITCH, IN PARTICULAR FOR A TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS 有权低电压隔离开关，特别适用于超声波应用的传输通道公开(公告)号：US20130265100A1
公开(公告)日：2013-10-10
申请号：US13907468
申请日：2013-05-31
发明人： Valeria Bottarel , Giulio Ricotti , Fabio Quaglia
IPC分类号： H03K17/16
CPC分类号： H03K17/16 , H03K17/08104 , H03K17/30
摘要： A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.
摘要翻译： 低压隔离开关适合于从连接节点接收高电压信号，并通过连接端将所述高电压信号发送到负载。 隔离开关包括连接在第一和第二参考电极之间的驱动块，并且包括耦合在第一电压基准（Vss）和第一驱动电路节点之间的第一驱动晶体管和耦合在驱动电路节点和第二驱动电路节点之间的第二驱动晶体管 电源参考电压。 开关包括连接到连接端子（pzt）的隔离块，连接节点和驱动中心电路节点，并且包括电压限制器块，二极管块和控制晶体管。 控制晶体管连接在连接节点和连接端子之间的二极管块两端，并具有连接到驱动中心电路节点的控制端子。
-
公开(公告)号：US20170257092A1
公开(公告)日：2017-09-07
申请号：US15216271
申请日：2016-07-21
发明人： Sandro Rossi , Valeria Bottarel
IPC分类号： H03K17/687 , H03K19/0175
CPC分类号： H03K17/687 , H03K3/3565 , H03K17/04123 , H03K17/063 , H03K17/6872 , H03K19/017509 , H03K19/018521 , H03K2217/0036 , H03K2217/0045
摘要： A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.
-
公开(公告)号：US09401799B2
公开(公告)日：2016-07-26
申请号：US14661937
申请日：2015-03-18
发明人： Juri Giovannone , Valeria Bottarel , Marco Terenzi , Sandro Rossi
CPC分类号： H04L7/0045 , H03K5/135 , H03K5/14 , H03L7/0814 , H04L7/0037
摘要： The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a synchronization signal. A digital delay corresponding to the time spread is applied to the synchronization signal. The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit that are applied to the synchronization signal.
摘要翻译： 表现出作为过程，电压和温度变化的函数的时间扩展的延迟的电路的操作与同步信号同步。 对应于时间扩展的数字延迟被施加到同步信号。 通过具有各自的延迟值的级联延迟元件和通过控制施加到同步信号的电路中的级联延迟元件的数量来产生数字延迟。
-
4.发明申请ENERGY HARVESTING SYSTEM WITH SELECTIVELY ACTIVATABLE HARVESTING INTERFACE, AND METHOD OF ENERGY HARVESTING 有权能量采集系统，具有选择性的捕获接口和能量采集方法公开(公告)号：US20140239917A1
公开(公告)日：2014-08-28
申请号：US14181270
申请日：2014-02-14
发明人： Valeria Bottarel , Giulio Ricotti
IPC分类号： H02J7/00
CPC分类号： H02J7/0052 , H02J7/32 , H02M1/36 , H02M2001/0032 , Y02B70/16
摘要： An energy-harvesting system includes a transducer to convert environmental energy into a harvesting electrical signal. A storage element stores electrical energy derived from conversion of the harvested environmental energy. A harvesting interface supplies an electrical charging signal to the storage element. The harvesting interface is selectively connected to the storage element in response to a control signal. The control signal causes the connection when the harvesting electrical signal exceeds a threshold. Conversely, the control signal causes the disconnection when the harvesting electrical signal is less than the threshold.
摘要翻译： 能量收集系统包括将环境能量转换成收获电信号的换能器。 存储元件存储从收获的环境能量的转化得到的电能。 收割界面向存储元件提供充电信号。 响应于控制信号，收获界面选择性地连接到存储元件。 当采集电信号超过阈值时，控制信号导致连接。 相反，当采集电信号小于阈值时，控制信号导致断开。
-
5.发明申请公开(公告)号：US20140104002A1
公开(公告)日：2014-04-17
申请号：US14052495
申请日：2013-10-11
发明人： Valeria Bottarel , Giulio Ricotti
IPC分类号： H03F3/45
CPC分类号： H03F3/45076 , H02M2001/0006 , H02N2/181
摘要： A differentiator generates a time derivative signal from a time-variable signal. A transconductance amplifier generates a biasing control signal as a function of the time derivative signal. A supply network functions to supply the differentiator and transconductance amplifier. The supply network is driven by the biasing control signal output from the transconductance amplifier. With this configuration, speed of operation of the differentiator and transconductance amplifier vary with the supply provided by the supply network, and the supply is modulated as a function of the received time-variable signal.
摘要翻译： 微分器从时间变量信号产生时间导数信号。 跨导放大器产生作为时间导数信号的函数的偏置控制信号。 供电网络用于提供微分器和跨导放大器。 供电网络由跨导放大器输出的偏置控制信号驱动。 利用这种配置，微分器和跨导放大器的操作速度随着供电网络的供给而变化，并且电源根据接收到的时间变量信号进行调制。
-
公开(公告)号：US12081122B2
公开(公告)日：2024-09-03
申请号：US17532867
申请日：2021-11-22
IPC分类号： H02M1/08 , H02M1/00 , H02M3/158 , H03K17/687
CPC分类号： H02M3/158 , H02M1/0006 , H02M1/08 , H03K17/687 , H03K2217/0081
摘要： In an embodiment, a switching converter includes: a switching stage configured to receive a direct current input voltage, receive a driving signal for driving the switching stage, and provide a direct current output voltage according to the input voltage and the driving signal; a driving stage configured to provide the driving signal to the switching stage; a current sensing circuit configure to sense an output current provided by the switching stage; and a voltage generation circuit configured to generate at least one supply voltage for powering the driving stage, and adjust the at least one supply voltage according to the output current.
-
7.发明授权公开(公告)号：US11881768B2
公开(公告)日：2024-01-23
申请号：US17364063
申请日：2021-06-30
CPC分类号： H02M3/04 , H03K5/131 , H03K5/14 , H03K2005/00058
摘要： A direct current (DC) to DC (DC-DC) converter includes a comparator configured to set a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL configured increase the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer configured to selectively output a delayed version of the signal pulse; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit configured to adaptively adjust a precision of the DC-DC converter in accordance with a duty cycle of the DC-DC converter and a setpoint of the DC-DC converter.
-
公开(公告)号：US11791720B2
公开(公告)日：2023-10-17
申请号：US17364147
申请日：2021-06-30
CPC分类号： H02M3/04 , H03K5/24 , G06F1/26 , H03K2005/00058
摘要： A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.
-
公开(公告)号：US20160036583A1
公开(公告)日：2016-02-04
申请号：US14661937
申请日：2015-03-18
发明人： Juri Giovannone , Valeria Bottarel , Marco Terenzi , Sandro Rossi
IPC分类号： H04L7/00
CPC分类号： H04L7/0045 , H03K5/135 , H03K5/14 , H03L7/0814 , H04L7/0037
摘要： The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a sync signal by applying to the sync signal a digital delay, which can add to the delay that is subject to time spread.The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit.
摘要翻译： 表现出作为过程，电压和温度变化的函数的时间扩展的延迟的电路的操作与同步信号同步，该同步信号通过向同步信号施加数字延迟，这可以增加延迟 受时间限制。 通过具有各自的延迟值的级联延迟元件和通过控制电路中的级联延迟元件的数量来产生数字延迟。
-
公开(公告)号：US11888384B2
公开(公告)日：2024-01-30
申请号：US17532833
申请日：2021-11-22
CPC分类号： H02M1/0006 , H02M3/158
摘要： In an embodiment, a switching converter includes: a switching stage including first and second switching devices for receiving an input voltage and for providing an output voltage; a driving stage including first and second driving devices for driving the first and second switching devices, respectively; a current sensing arrangement for sensing an output current provided by the switching stage; a voltage generation arrangement configured to generate a supply voltage for powering the driving stage, the voltage generation arrangement being configured to adjust the supply voltage according to the sensed output current; and a charge recovery stage configured to store a first electric charge being lost from the first driving device during driving of the first switching device and to release at least partially the stored first electric charge to the second driving device during driving of the second switching device.
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.017 秒)
