公开(公告)号：US09025355B2

公开(公告)日：2015-05-05

申请号：US13954908

申请日：2013-07-30

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics PVT Ltd

Inventor： Fabio De Santis ,  Marco Pasotti ,  Abhishek Lal

IPC: G11C5/06 ,  G11C5/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。

公开(公告)号：US20150228338A1

公开(公告)日：2015-08-13

申请号：US14175843

申请日：2014-02-07

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics International NV

Inventor： BharathManoj Manda ,  Abhishek Lal ,  Marco Pasotti ,  Marcella Carissimi

IPC: G11C13/00 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2029/0411 ,  G11C2211/5646

Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

Abstract translation: 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。