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公开(公告)号：US20180243791A1
公开(公告)日：2018-08-30
申请号：US15691292
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Ugo Ghisu , Sandro Rossi , Andrea Gambero
Abstract: A circuit for an ultrasonic channel has a first and a second terminal between which extend a resistive and diode signal paths including a pair of diodes with opposing polarities, for example in anti-parallel. Switching circuitry is coupled with the resistive and diode signal paths and is switchable between first and second states. In the first state, the first and the second terminals are coupled with one another via the resistive signal path. In the second state, the first and the second terminals are coupled with one another via the diode signal path. The switching circuitry includes first and second transistor discharge circuits coupled between first and second drive lines and current paths of these transistors, and coupled to control terminals of these transistors. The control terminals are coupled to the first or second drive line and are non-conductive and conductive in first and second operating states, respectively.
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Patent Agency Ranking
公开(公告)号：US10730073B2
公开(公告)日：2020-08-04
申请号：US15691292
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Ugo Ghisu , Sandro Rossi , Andrea Gambero
Abstract: A circuit for an ultrasonic channel has a first and a second terminal between which extend a resistive and diode signal paths including a pair of diodes with opposing polarities, for example in anti-parallel. Switching circuitry is coupled with the resistive and diode signal paths and is switchable between first and second states. In the first state, the first and the second terminals are coupled with one another via the resistive signal path. In the second state, the first and the second terminals are coupled with one another via the diode signal path. The switching circuitry includes first and second transistor discharge circuits coupled between first and second drive lines and current paths of these transistors, and coupled to control terminals of these transistors. The control terminals are coupled to the first or second drive line and are non-conductive and conductive in first and second operating states, respectively.
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公开(公告)号：US20180248544A1
公开(公告)日：2018-08-30
申请号：US15690963
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Ugo Ghisu , Sandro Rossi , Andrea Gambero
IPC: H03K17/567 , H03K5/08 , A61B8/00
CPC classification number: H03K17/567 , A61B8/54 , B06B1/0215 , B06B2201/77 , H03K5/023 , H03K5/08
Abstract: A driver circuit for driving, for example, ultrasonic transducers in medical equipment, such as ultrasound scanning equipment. The driver circuit includes first inputs receptive of a pulsed signal, second inputs receptive of an analog signal, an output for applying a pulsed drive signal or an analog drive signal to a load. A pair of output transistors of complementary polarities are positioned with their current paths in series between opposing supply lines with a connection point intermediate between the transistors of the pair of transistors. The connection point between output transistors is coupled to the output of the circuit. The control terminals of the output transistors, which are coupled together, may be coupled to the first inputs with the driver functioning as a pulser, or else coupled to the second inputs with the driver functioning as a linear driver.
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公开(公告)号：US20240361800A1
公开(公告)日：2024-10-31
申请号：US18631738
申请日：2024-04-10
Applicant: STMicroelectronics S.r.l.
Inventor： Juri Giovannone , Roberto Giorgio Bardelli , Andrea Gambero , Alessio Corso , Donata Rosaria Maria Nicolosi
CPC classification number: G06F1/10 , G04F10/005 , G06F1/12 , H03K5/00 , H03K2005/00013
Abstract: The present invention relates to a system and a method for generating a plurality of control signals for multi-die applications. In particular, the invention relates to the generation of synchronized control signals generated by independent dies having an own local clock and provided with a common clock. In a first step, in each die, the period of the common clock signal is measured using a TDC. In further steps, in each die, a respective phase shift is evaluated and applied between the rising edge of the common clock signal and each of the rising edges of the output control signals, using delay unit.
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公开(公告)号：US10734954B2
公开(公告)日：2020-08-04
申请号：US15691298
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Gambero , Davide Ugo Ghisu , Sandro Rossi
Abstract: An operational amplifier including an input stage coupled to an input terminal, an output stage coupled to an output terminal, and a gain node between the input stage and the output stage. A bias current source is couplable to the input stage to supply a bias current thereto and a current mirror circuit mirrors the bias current toward the gain node and the output stage. A switch circuit includes a switch activatable to bring the gain node to a pre-bias voltage and a switch coupled to the output stage and switchable between a first state and a second state in which the output stage is active and non-active, respectively—. A further switch circuit is coupled to the output terminal and switchable between a first state and a second state in which the output stage is coupled to the output terminal and to a reference level, respectively.
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公开(公告)号：US20180248522A1
公开(公告)日：2018-08-30
申请号：US15691298
申请日：2017-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Gambero , Davide Ugo Ghisu , Sandro Rossi
CPC classification number: H03F1/305 , H03F1/307 , H03F3/187 , H03F3/217 , H03F3/302 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2200/297 , H03F2200/516 , H03F2203/30099 , H03F2203/30132 , H04R3/00
Abstract: An operational amplifier including an input stage coupled to an input terminal, an output stage coupled to an output terminal, and a gain node between the input stage and the output stage. A bias current source is couplable to the input stage to supply a bias current thereto and a current mirror circuit mirrors the bias current toward the gain node and the output stage. A switch circuit includes a switch activatable to bring the gain node to a pre-bias voltage and a switch coupled to the output stage and switchable between a first state and a second state in which the output stage is active and non-active, respectively—. A further switch circuit is coupled to the output terminal and switchable between a first state and a second state in which the output stage is coupled to the output terminal and to a reference level, respectively.
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