公开(公告)号：US20190130970A1

公开(公告)日：2019-05-02

申请号：US16169763

申请日：2018-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Marco Pasotti ,  Chantal Auricchio

IPC: G11C13/00

Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.

公开(公告)号：US11798603B2

公开(公告)日：2023-10-24

申请号：US18175375

申请日：2023-02-27

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Vivek Tyagi ,  Vikas Rana ,  Chantal Auricchio ,  Laura Capecchi

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/222 ,  G11C11/4091 ,  G11C11/4094

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US11615823B2

公开(公告)日：2023-03-28

申请号：US17542203

申请日：2021-12-03

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vivek Tyagi ,  Vikas Rana ,  Chantal Auricchio ,  Laura Capecchi

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US10755777B2

公开(公告)日：2020-08-25

申请号：US16169763

申请日：2018-10-24

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Marco Pasotti ,  Chantal Auricchio

IPC: G11C13/00 ,  H01L45/00 ,  G11C5/02 ,  H01L27/24 ,  G11C17/12 ,  G11C5/06

Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.

公开(公告)号：US10068643B2

公开(公告)日：2018-09-04

申请号：US15422290

申请日：2017-02-01

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Marco Pasotti ,  Marcella Carissimi ,  Rajat Kulshrestha ,  Chantal Auricchio

IPC: G11C13/00 ,  G11C7/08 ,  G11C7/06

Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.

公开(公告)号：US11798630B2

公开(公告)日：2023-10-24

申请号：US17407903

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Fabio Enrico Carlo Disegni ,  Chantal Auricchio ,  Cesare Torti ,  Davide Manfre' ,  Laura Capecchi ,  Emanuela Calvetti ,  Stefano Zanchi

IPC: G11C16/28 ,  G11C16/10 ,  G11C7/04 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C7/04 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

公开(公告)号：US11205462B2

公开(公告)日：2021-12-21

申请号：US17010704

申请日：2020-09-02

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Vivek Tyagi ,  Vikas Rana ,  Chantal Auricchio ,  Laura Capecchi

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/22

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

公开(公告)号：US09613692B1

公开(公告)日：2017-04-04

申请号：US14971488

申请日：2015-12-16

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Marco Pasotti ,  Marcella Carissimi ,  Rajat Kulshrestha ,  Chantal Auricchio

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/065 ,  G11C7/08 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0042 ,  G11C2207/002

Abstract: A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.