公开(公告)号：US10211059B2

公开(公告)日：2019-02-19

申请号：US15601115

申请日：2017-05-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L21/28

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US09691871B1

公开(公告)日：2017-06-27

申请号：US14973825

申请日：2015-12-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L21/76 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US20170179250A1

公开(公告)日：2017-06-22

申请号：US14973825

申请日：2015-12-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US20170256625A1

公开(公告)日：2017-09-07

申请号：US15601115

申请日：2017-05-22

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Pierre Caubet ,  Florian Domengie ,  Carlos Augusto Suarez Segovia ,  Aurelie Bajolet ,  Onintza Ros Bengoechea

IPC: H01L29/49 ,  H01L29/40

CPC classification number: H01L21/28088 ,  H01L29/4966

Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.

公开(公告)号：US09530489B2

公开(公告)日：2016-12-27

申请号：US14527166

申请日：2014-10-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre Caubet ,  Mickael Gros-Jean

IPC: G11C7/00 ,  G11C11/42 ,  G11C13/04 ,  G02F1/163 ,  G02F1/15 ,  G02F3/02

CPC classification number: G11C11/42 ,  G02F1/15 ,  G02F1/1523 ,  G02F1/1525 ,  G02F1/1527 ,  G02F1/163 ,  G02F3/022 ,  G02F2001/1512 ,  G02F2001/1635 ,  G02F2201/58 ,  G11C7/00 ,  G11C13/04

Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.

Abstract translation: 存储器件可以包括存取晶体管，以及被配置为存储信息项的存储单元。 存储单元可以包括被配置为具有分别对应于信息项的两个值的不同光电子状态的第一和第二电极，以及基于存储单元外部的控制信号在不同的光电子态之间切换，不同的光电子态是 在没有控制信号的情况下自然稳定。 存储单元还可以包括在第一和第二电极之间的固体电解质。

公开(公告)号：US09257518B2

公开(公告)日：2016-02-09

申请号：US14254994

申请日：2014-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Baudot ,  Pierre Caubet ,  Florian Domengie

IPC: H01L21/00 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/78

Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.

Abstract translation: 至少一个MOS晶体管是通过在衬底上形成电介质区域并在电介质区域上形成栅极来制造的。 栅极形成为包括金属栅极区域。 金属栅极区域的形成包括：形成第一材料层，其被配置为降低晶体管的阈值电压的绝对值，并且构成金属栅极区域的一部分，以便在层的上方形成扩散阻挡层 第一种材料。 然后，使用掺杂剂激活退火形成掺杂源极和漏极区。

公开(公告)号：US20140319616A1

公开(公告)日：2014-10-30

申请号：US14254994

申请日：2014-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Baudot ,  Pierre Caubet ,  Florian Domengie

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/42372 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/78

Abstract: At least one MOS transistor is produced by forming a dielectric region above a substrate and forming a gate over the dielectric region. The gate is formed to include a metal gate region. Formation of the metal gate region includes: forming a layer of a first material configured to reduce an absolute value of a threshold voltage of the transistor, and configuring a part of the metal gate region so as also to form a diffusion barrier above the layer of the first material. Then, doped source and drain regions are formed using a dopant activation anneal.

Abstract translation: 至少一个MOS晶体管是通过在衬底上形成电介质区域并在电介质区域上形成栅极来制造的。 栅极形成为包括金属栅极区域。 金属栅极区域的形成包括：形成第一材料层，其被配置为降低晶体管的阈值电压的绝对值，并且构成金属栅极区域的一部分，以便在层的上方形成扩散阻挡层 第一种材料。 然后，使用掺杂剂激活退火形成掺杂源极和漏极区。

公开(公告)号：US09953837B2

公开(公告)日：2018-04-24

申请号：US14669183

申请日：2015-03-26

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre Caubet ,  Sylvain Baudot

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/285

CPC classification number: H01L21/28088 ,  H01L21/28158 ,  H01L21/28556 ,  H01L29/4966

Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.

公开(公告)号：US09536599B1

公开(公告)日：2017-01-03

申请号：US15249583

申请日：2016-08-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre Caubet ,  Mickael Gros-Jean

IPC: G11C7/00 ,  G11C11/42 ,  G11C13/04 ,  G02F1/15

CPC classification number: G11C11/42 ,  G02F1/15 ,  G02F1/1523 ,  G02F1/1525 ,  G02F1/1527 ,  G02F1/163 ,  G02F3/022 ,  G02F2001/1512 ,  G02F2001/1635 ,  G02F2201/58 ,  G11C7/00 ,  G11C13/04

Abstract: A memory device may include an access transistor, and a memory cell configured to store an item of information. The memory cell may include first and second electrodes configured to have different optoelectronic states corresponding respectively to two values of the item of information, and to switch between the different optoelectronic states based upon a control signal external to the memory cell, the different optoelectronic states being naturally stable in an absence of the control signal. The memory cell may also include a solid electrolyte between the first and second electrodes.

Abstract translation: 存储器件可以包括存取晶体管，以及被配置为存储信息项的存储单元。 存储单元可以包括被配置为具有分别对应于信息项的两个值的不同光电子状态的第一和第二电极，以及基于存储单元外部的控制信号在不同的光电子态之间切换，不同的光电子态是 在没有控制信号的情况下自然稳定。 存储单元还可以包括在第一和第二电极之间的固体电解质。

公开(公告)号：US09029254B2

公开(公告)日：2015-05-12

申请号：US14032436

申请日：2013-09-20

Applicant: STMicroelectronics Crolles 2 SAS

Inventor： Pierre Caubet ,  Florian Domengie ,  Sylvain Baudot

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/02266 ,  H01L21/02697 ,  H01L21/28088 ,  H01L29/66477

Abstract: A method for forming an aluminum titanium nitride layer on a wafer by plasma-enhanced physical vapor deposition including a first step at a radio frequency power ranging between 100 and 500 W only, and a second step at a radio frequency power ranging between 500 and 1,000 W superimposed to a D.C. power ranging between 500 and 1,000 W. An insulated gate comprising such an aluminum titanium nitride layer.

Abstract translation: 一种通过等离子体增强物理气相沉积在晶片上形成氮化铝钛层的方法，其包括仅在100至500W之间的射频功率范围内的第一步骤，以及范围在500和1,000之间的射频功率的第二步骤 W叠加到500和1,000W之间的DC功率。包括这种铝氮化钛层的绝缘栅极。