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    Circuit and method for skew correction
    1.
    发明授权
    Circuit and method for skew correction 有权
    用于偏斜校正的电路和方法

    公开(公告)号：US09000963B2

    公开(公告)日：2015-04-07

    申请号：US14293119

    申请日：2014-06-02

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Pratap Narayan Singh ,  Stéphane Le Tual

    IPC: H03M1/00 ,  H03K17/22 ,  H03M1/12 ,  H03K17/14 ,  H03K17/687

    CPC classification number: H03K17/223 ,  H03K17/145 ,  H03K17/687 ,  H03K2217/0018 ,  H03M1/12

    Abstract: The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.

    Abstract translation: 本发明涉及一种电路，包括：具有第一和第二主电流节点的第一晶体管（102）和适于接收用于使第一晶体管在导通状态与非导通状态之间转变的第一定时信号（CLK）的栅极节点; 偏置电路（108），耦合到所述第一晶体管的另一节点; 以及适于控制所述偏置电路以对所述另一节点施加第一控制电压（VCTRL）以调整至少一个所述转换的定时的控制电路（110）。

    Variable Delay Element
    2.
    发明申请
    Variable Delay Element 有权
    可变延迟元件

    公开(公告)号：US20150028930A1

    公开(公告)日：2015-01-29

    申请号：US14337896

    申请日：2014-07-22

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

    IPC: H03H11/26

    CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

    Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

    Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

    Circuit and method for signal conversion
    3.
    发明授权
    Circuit and method for signal conversion 有权
    电路和信号转换方法

    公开(公告)号：US09000964B2

    公开(公告)日：2015-04-07

    申请号：US14294300

    申请日：2014-06-03

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

    IPC: H03M1/00 ,  H03M1/08 ,  H03K3/013 ,  G11C27/02 ,  H03K19/0185

    CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

    Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CNGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

    Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CNGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

    Variable delay element
    4.
    发明授权
    Variable delay element 有权
    可变延迟元件

    公开(公告)号：US09432008B2

    公开(公告)日：2016-08-30

    申请号：US14337896

    申请日：2014-07-22

    Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

    Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

    IPC: H03K5/13 ,  H03K5/134 ,  H03K5/00

    CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

    Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

    Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

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