公开(公告)号：US09171999B2

公开(公告)日：2015-10-27

申请号：US13907132

申请日：2013-05-31

Applicant: Samsung Display Co., Ltd.

Inventor： Chang-Oh Jeong ,  Woo-Sung Sohn ,  Dong-Gyu Kim ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jean-Ho Song

IPC: H01L27/01 ,  H01L33/16 ,  H01L27/12

CPC classification number: H01L33/16 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

Abstract translation: 提供了一种薄膜晶体管阵列面板，包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，以及设置在半导体层上的数据线和漏电极。 数据线和漏电极具有包括下层和上层的双层结构，其中下层具有突出于上层之外的第一部分，并且半导体层具有突出于下层边缘外侧的第二部分 。

公开(公告)号：US09570477B2

公开(公告)日：2017-02-14

申请号：US15041746

申请日：2016-02-11

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwang-Ho Lee ,  Jang-Soo Kim ,  Hong-Suk Yoo ,  Sang-Soo Kim ,  Shi-Yul Kim ,  Jae-Hyoung Youn

IPC: H01L33/00 ,  H01L21/28 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1339

CPC classification number: H01L27/124 ,  G02F1/13394 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.

Abstract translation: 薄膜晶体管（“TFT”）阵列面板包括： 绝缘基板，设置在所述绝缘基板上并包括漏电极的TFT，覆盖所述TFT的钝化层，并且包括设置在其中的所述漏电极对应的接触部分，所述隔板包括设置在所述钝化层上的有机材料，并且包括 横向部分，纵向部分和设置在漏电极上的接触部分，设置在钝化层上并设置在由隔板限定的区域中的滤色器，设置在隔板上的有机覆盖层和滤色器，以及 设置在所述有机覆盖层上的像素电极，并且通过所述钝化层的接触部分和所述隔离物的接触部分连接到所述漏电极，其中在所述有机覆盖层中形成接触孔，所述接触孔对应于所述钝化层的接触部分 钝化层。

公开(公告)号：US09443881B2

公开(公告)日：2016-09-13

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jean-Ho Song ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L29/04 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。

公开(公告)号：US09269729B2

公开(公告)日：2016-02-23

申请号：US14727286

申请日：2015-06-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwang-Ho Lee ,  Jang-Soo Kim ,  Hong-Suk Yoo ,  Sang-Soo Kim ,  Shi-Yul Kim ,  Jae-Hyoung Youn

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1339

CPC classification number: H01L27/124 ,  G02F1/13394 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.

公开(公告)号：US20150053984A1

公开(公告)日：2015-02-26

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JEAN-HO SONG ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。

公开(公告)号：US08785934B2

公开(公告)日：2014-07-22

申请号：US13677176

申请日：2012-11-14

Applicant: Samsung Display Co., Ltd.

Inventor： Sang-Woo Whangbo ,  Shi-Yul Kim ,  Sung-Hoon Yang ,  Woo-Geun Lee

IPC: H01L29/04 ,  H01L29/10

CPC classification number: H01L29/4908 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin film transistor substrate includes a base substrate, a gate electrode, a gate insulating layer, a surface treating layer, an active layer, a source electrode and a drain electrode. The gate electrode is formed on the base substrate. The gate insulating layer is formed on the base substrate to cover the gate electrode. The surface treating layer is formed on the gate insulating layer by treating the gate insulating layer with a nitrogen-containing gas to prevent leakage current. The active layer is formed on the surface treating layer to cover the gate electrode. The source electrode and the gate electrode that are spaced apart from each other by a predetermined distance are formed on the active layer.

Abstract translation: 薄膜晶体管基板包括基底基板，栅极电极，栅极绝缘层，表面处理层，有源层，源电极和漏电极。 栅电极形成在基底基板上。 栅极绝缘层形成在基底基板上以覆盖栅电极。 通过用含氮气体处理栅极绝缘层，在栅极绝缘层上形成表面处理层，以防止漏电流。 在表面处理层上形成有源层以覆盖栅电极。 在有源层上形成彼此隔开预定距离的源电极和栅电极。