公开(公告)号：US20250070765A1

公开(公告)日：2025-02-27

申请号：US18813909

申请日：2024-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K3/3562 ,  H03K3/012

Abstract: A flip-flop is provided. The flip-flop includes: a master latch; and a slave latch. The master latch includes: a first circuit configured to, based on a clock signal, a data input signal, and a first data signal, generate a second data signal complementary to the data input signal; a second circuit configured to, based on the clock signal, an inverted data input signal, and the second data signal, generate the first data signal complementary to the inverted data input signal; and a third circuit configured to generate a latch signal based on the clock signal, an input of the slave latch, and the second data signal. The slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal.

公开(公告)号：US20170019123A1

公开(公告)日：2017-01-19

申请号：US15097715

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mooyeol Choi ,  Hyungdong Roh ,  Bai-Sun Kong ,  Sunwoo Kwon ,  Myung-Jin Lee

IPC: H03M3/00 ,  G06F3/16

CPC classification number: H03M3/422 ,  G06F3/162 ,  H03M1/464 ,  H03M3/372 ,  H03M3/50

Abstract: A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.

Abstract translation: Δ-Σ调制器包括环路滤波器，被配置为将模拟输出信号改变为数字信号的量化器，以及被配置为接收数字信号并包括第一电容器和第二电容器的数/模转换器。 在第一采样周期中，第一电容器被放电，同时第二电容器被充以基准电压。 在第二采样周期中，数字信号包括由时钟抖动引起的噪声，第一电容器用参考电压充电，并且第二电容器被放电并产生对应于噪声的电荷。 在接下来的第一采样周期中，第一电容器被放电，并且同时第二电容器使用电荷产生与噪声相对应的噪声电流并且对基准电压进行充电。

公开(公告)号：US09742428B2

公开(公告)日：2017-08-22

申请号：US15097715

申请日：2016-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mooyeol Choi ,  Hyungdong Roh ,  Bai-Sun Kong ,  Sunwoo Kwon ,  Myung-Jin Lee

IPC: G06F17/00 ,  H03M3/00 ,  G06F3/16

CPC classification number: H03M3/422 ,  G06F3/162 ,  H03M1/464 ,  H03M3/372 ,  H03M3/50

Abstract: A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.

公开(公告)号：US20250080119A1

公开(公告)日：2025-03-06

申请号：US18818024

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K23/56 ,  H03K23/44 ,  H03M1/48

Abstract: Disclosed are a bidirectional counter and a method of generating output data. The bidirectional counter may include at least one first flip-flop configured to generate, based on at least one first local clock, at least one first bit including a least significant bit (LSB) of the output data and a second bit that is an upper bit of the at least one first bit, and a local clock generation circuit configured to generate, in response to an up signal that is activated, the at least one first local clock based on the input clock and the at least one first bit, and to generate, in response to the up signal that is deactivated, the at least one first local clock based on the input clock and at least one inverted first bit.

公开(公告)号：US09276574B2

公开(公告)日：2016-03-01

申请号：US13890517

申请日：2013-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoi-jin Lee ,  Bai-Sun Kong

IPC: H03K19/003 ,  H03K3/356

CPC classification number: H03K19/003 ,  H03K3/356182

Abstract: A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode.

Abstract translation: 扫描触发器电路包括输入单元和输出单元。 数据输出单元被配置为在第一操作模式中响应于数据输入信号和第一控制信号向数据输出端提供数据输出信号，并且数据输出单元被配置为禁止数据输出端 在第二操作模式中响应于数据输入信号和第一控制信号，提供施加到扫描触发器电路的电源电压和接地电压。 扫描输出单元被配置为在第二操作模式中响应于扫描输入信号和第二控制信号向扫描输出端提供扫描输出信号。

公开(公告)号：US20250070763A1

公开(公告)日：2025-02-27

申请号：US18812395

申请日：2024-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Bai-Sun Kong ,  Bomin Joo

IPC: H03K3/037

Abstract: A flip-flop configured to generate an output toggling according to an input clock includes an inverter configured to generate the output by inverting a first data signal, a first circuit configured to generate a second data signal based on an input clock and a latch signal, a second circuit configured to generate the latch signal based on the input clock and the second data signal, and a third circuit configured to generate the first data signal using the input clock, the second data signal, and the latch signal, wherein the third circuit is further configured to pull down the first data signal, independently of the second data signal, using the input clock and the latch signal.