公开(公告)号：US09853111B2

公开(公告)日：2017-12-26

申请号：US15174412

申请日：2016-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Bon Young Koo ,  Hyun Gi Hong

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/08 ,  H01L29/40 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a gate structure, the gate structure extending in a direction intersecting with a direction in which the active fins extend; forming an etch stop layer on the source/drain regions; forming an interlayer dielectric layer on the etch stop layer; forming a first opening by partially removing the interlayer dielectric layer so as not to expose the etch stop layer; forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening; forming a second opening by removing the impurity region so as to expose the etch stop layer; implanting a second impurity ion into the exposed etch stop layer; and removing the exposed etch stop layer.

公开(公告)号：US09390977B2

公开(公告)日：2016-07-12

申请号：US14825556

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Jong Han ,  Bon Young Koo ,  Ki Yeon Park ,  Jae Young Park ,  Sun Young Lee ,  Kyung In Choi

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/76224

Abstract: A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底中形成限定多个活性鳍片的沟槽，在多个活性鳍片上形成牺牲层，形成牺牲氧化物层，以及去除牺牲氧化物层。 形成牺牲氧化物层包括热处理牺牲层和多个活性鳍片的表面。

公开(公告)号：US09859387B2

公开(公告)日：2018-01-02

申请号：US14990793

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum Kim ,  Chul Sung Kim ,  Kang Hun Moon ,  Yang Xu ,  Bon Young Koo

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66 ,  H01L27/11 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/41791 ,  H01L27/1104 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

公开(公告)号：US20160359008A1

公开(公告)日：2016-12-08

申请号：US15174412

申请日：2016-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung In Choi ,  Bon Young Koo ,  Hyun Gi Hong

IPC: H01L29/417 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/41791 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of manufacturing a semiconductor device includes forming active fins on a substrate; forming source/drain regions on the active fins on both sides of a gate structure, the gate structure extending in a direction intersecting with a direction in which the active fins extend; forming an etch stop layer on the source/drain regions; forming an interlayer dielectric layer on the etch stop layer; forming a first opening by partially removing the interlayer dielectric layer so as not to expose the etch stop layer; forming an impurity region within the interlayer dielectric layer by implanting a first impurity ion through the first opening; forming a second opening by removing the impurity region so as to expose the etch stop layer; implanting a second impurity ion into the exposed etch stop layer; and removing the exposed etch stop layer.

Abstract translation: 半导体器件的制造方法包括：在基板上形成有源翅片; 在栅极结构两侧的活性鳍片上形成源极/漏极区域，栅极结构在与活性鳍片延伸的方向相交的方向上延伸; 在源/漏区上形成蚀刻停止层; 在所述蚀刻停止层上形成层间介质层; 通过部分去除所述层间电介质层以形成不暴露所述蚀刻停止层而形成第一开口; 通过在第一开口中注入第一杂质离子，在层间电介质层内形成杂质区; 通过去除杂质区域形成第二开口以暴露蚀刻停止层; 将第二杂质离子注入到暴露的蚀刻停止层中; 并去除暴露的蚀刻停止层。