MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号:US20190214091A1

    公开(公告)日:2019-07-11

    申请号:US16047384

    申请日:2018-07-27

    Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

    Nonvolatile memory device and program method and program verification method thereof

    公开(公告)号:US10061633B2

    公开(公告)日:2018-08-28

    申请号:US15155162

    申请日:2016-05-16

    CPC classification number: G11C11/5628 G11C16/0483 G11C16/10 G11C16/3459

    Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

    Nonvolatile memory device
    4.
    发明授权

    公开(公告)号:US11756613B2

    公开(公告)日:2023-09-12

    申请号:US17901308

    申请日:2022-09-01

    Abstract: A memory device includes: a first substrate; a peripheral circuit provided on the first substrate; a first metal bonding layer provided on the peripheral circuit; a second metal bonding layer directly bonded to the first metal bonding layer; a memory cell array provided on the second metal bonding layer; and a second substrate provided on the memory cell array. A page buffer circuit in the peripheral circuit receives a verification result through the metal bonding layers, divides the verification result into stages, and sequentially outputs the verification result for the division into the stages, and a pass/failure checker in the peripheral circuit sequentially performs a counting operation about each of the stages to generate accumulated values, and compares the accumulated values and a reference value which increases from an initial value as the counting operation is performed, and the initial value is set by an external memory controller.

    Nonvolatile memory device and operating method thereof
    6.
    发明授权
    Nonvolatile memory device and operating method thereof 有权
    非易失性存储器件及其操作方法

    公开(公告)号:US09349482B2

    公开(公告)日:2016-05-24

    申请号:US14639331

    申请日:2015-03-05

    CPC classification number: G11C16/3459 G11C11/5628 G11C16/107 G11C16/26

    Abstract: A method of programming a nonvolatile memory device is provided which includes applying a program voltage to selected ones of a plurality of memory cells; applying a selected one of a plurality of verification voltages after pre-charging bit lines connected to memory cells to which the program voltage is applied; sensing the memory cells to which the selected verification voltage is applied; selecting memory cells programmed to a target state referring to the sensing result and target state data; and determining whether programming of the selected memory cells is passed or failed.

    Abstract translation: 提供了一种编程非易失性存储器件的方法,其包括将编程电压施加到多个存储器单元中的选定的存储器单元; 在连接到应用了编程电压的存储单元的位线预充电之后施加多个验证电压中的选定的一个; 感测所选择的验证电压被施加到的存储器单元; 参考感测结果和目标状态数据选择被编程到目标状态的存储器单元; 以及确定所选择的存储器单元的编程是否通过或失败。

    Memory device for changing pass voltage

    公开(公告)号:US11127472B2

    公开(公告)日:2021-09-21

    申请号:US16806535

    申请日:2020-03-02

    Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

    Nonvolatile memory device storing data in sub-blocks and operating method thereof

    公开(公告)号:US10902922B2

    公开(公告)日:2021-01-26

    申请号:US16412953

    申请日:2019-05-15

    Abstract: A nonvolatile memory includes a first sub-block defined by a first string select line and a first word line; a second sub-block defined by a second string select line different from the first string select line and a second word line different from the first word line; a first vacant block defined by the first string select line and the second word line; and a second vacant block defined by the second string select line and the first word line. First data is programmed in the first sub-block with, second data is programmed in the second sub-block, and no data is programmed in the first vacant block and the second vacant block.

    Nonvolatile memory device and program method and program verification method thereof

    公开(公告)号:US10777264B2

    公开(公告)日:2020-09-15

    申请号:US16108408

    申请日:2018-08-22

    Abstract: A program verification method for a nonvolatile memory device includes performing a first failure bit counting operation about a first stage to generate a first failure bit accumulated value and comparing the first failure bit accumulated value and a first failure reference value to determine a program failure. When the first failure bit accumulated value is less than the first failure reference value, a second failure bit counting operation for a second stage is performed to generate a second failure bit accumulated value. The second failure bit accumulated value is compared to a second reference value to determine a program failure. The second failure reference value is different from the first failure reference value.

    Memory device including a deterioration level detection circuit

    公开(公告)号:US10607705B2

    公开(公告)日:2020-03-31

    申请号:US16047384

    申请日:2018-07-27

    Abstract: A memory device includes a voltage generator that provides a read voltage to a selected word line and provides a pass voltage to a plurality of unselected word lines, and a deterioration level detection circuit. The selected word line and the unselected word lines are connected to a plurality of memory cells. The deterioration level detection circuit detects a deterioration level of memory cells connected to the selected word line based on data of memory cells that receive the read voltage. The memory cells connected to the selected word line and the memory cells that receive the read voltage are included in the plurality of memory cells. The voltage generator changes the pass voltage provided to the unselected word lines based on the deterioration level.

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