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公开(公告)号：US10546844B2
公开(公告)日：2020-01-28
申请号：US15342689
申请日：2016-11-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Choon Kim , Eon-Soo Jang , Eun-Hee Jung , Hyon-Chol Kim , Byeong-Yeon Cho
IPC: H01L23/498 , H01L21/48 , H01L25/10 , H01L25/00
Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.
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2.发明公开公开(公告)号：US20240321842A1
公开(公告)日：2024-09-26
申请号：US18733450
申请日：2024-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tong-Suk Kim , Byeong-Yeon Cho
CPC classification number: H01L25/105 , G11C5/025 , G11C5/04 , H01L24/19 , H01L24/20 , H01L25/50 , H01L24/13 , H01L24/48 , H01L2224/04105 , H01L2224/12105 , H01L2224/13111 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/1434 , H01L2924/15311 , H01L2924/15331 , H01L2924/181
Abstract: A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area.
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