公开(公告)号：US11107743B2

公开(公告)日：2021-08-31

申请号：US16673127

申请日：2019-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Tae Hwang ,  Jae-Choon Kim ,  Kyung-Suk Oh ,  Woon-Bae Kim ,  Jae-Min Jung

IPC: H01L23/31 ,  H01L23/498 ,  H05K1/14

Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

公开(公告)号：US10546844B2

公开(公告)日：2020-01-28

申请号：US15342689

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Choon Kim ,  Eon-Soo Jang ,  Eun-Hee Jung ,  Hyon-Chol Kim ,  Byeong-Yeon Cho

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00

Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

公开(公告)号：US11756850B2

公开(公告)日：2023-09-12

申请号：US17462269

申请日：2021-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Tae Hwang ,  Jae-Choon Kim ,  Kyung-Suk Oh ,  Woon-Bae Kim ,  Jae-Min Jung

IPC: H01L23/31 ,  H01L23/498 ,  H05K1/14

CPC classification number: H01L23/3135 ,  H01L23/4985 ,  H01L23/49838 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10128

Abstract: A chip on film package includes: a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

公开(公告)号：US09704815B2

公开(公告)日：2017-07-11

申请号：US15156327

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Na Choi ,  Young-Deuk Kim ,  Jae-Choon Kim ,  Eon-Soo Jang ,  Hee-Jung Hwang

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/45099

Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.

公开(公告)号：US20200303276A1

公开(公告)日：2020-09-24

申请号：US16673127

申请日：2019-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Tae Hwang ,  Jae-Choon Kim ,  Kyung-Suk Oh ,  Woon-Bae Kim ,  Jae-Min Jung

IPC: H01L23/31 ,  H01L23/498 ,  H05K1/14

Abstract: A chip on film package includes; a flexible base film having a first surface and a second surface opposite to each other, and having a chip mounting region on the first surface; a plurality of wirings extending in a first direction toward the chip mounting region; a semiconductor chip mounted in the chip mounting region on the first surface of the base film and electrically connected to the wirings; a pair of first heat dissipation members on the first surface of the base film and spaced apart from the semiconductor chip, and extending in a second direction perpendicular to the first direction; and a second heat dissipation member on the first surface of the base film and covering the semiconductor chip and the pair of first heat dissipation members.

公开(公告)号：US10707196B2

公开(公告)日：2020-07-07

申请号：US16162598

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Choon Kim ,  Young-Deuk Kim ,  Woo-Hyun Park

IPC: H01L23/02 ,  H01L25/18 ,  H05K1/18 ,  H01L23/427 ,  H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L23/367

Abstract: An electronic device includes a substrate, a first electronic product arranged on the substrate, a second electronic product arranged on the substrate to be spaced apart from the first electronic product, and a heat dissipating assembly covering the first and second electronic products, the heat dissipating assembly comprising a heat dissipating chamber including a hermetically sealed space having a first portion having one or more gaps in which a flowable heat dissipation fluid is disposed and having a second portion in which a solid thermal conductive member is disposed to prevent the flow of the heat dissipation fluid across the second portion with respect to a plan view, wherein the first portion of the heat dissipating chamber has a first thermal conductivity and overlaps with the first electronic product in the plan view, wherein the solid thermal conductive member has a second thermal conductivity less than the first thermal conductivity, wherein the solid thermal conductive member overlaps with the second electronic product in the plan view, wherein the overlapping area of the solid thermal conductive member with the second electronic product is greater than 50% of an area of the second electronic product in the plan view.