公开(公告)号：US10546844B2

公开(公告)日：2020-01-28

申请号：US15342689

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Choon Kim ,  Eon-Soo Jang ,  Eun-Hee Jung ,  Hyon-Chol Kim ,  Byeong-Yeon Cho

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/10 ,  H01L25/00

Abstract: In a method of manufacturing a stack package, a first semiconductor chip is formed on a first package substrate. A second semiconductor chip is formed on a second package substrate. A plurality of signal pads and a thermal diffusion member are formed on a lower surface and/or an upper surface of an interposer substrate, the signal pad having a first height and the thermal diffusion member having a second height greater than the first height. The first package substrate, the interposer substrate, and the second package substrate are sequentially stacked on one another such that the thermal diffusion member is in contact with an upper surface of the first semiconductor chip or a lower surface of the second package substrate.

公开(公告)号：US09704815B2

公开(公告)日：2017-07-11

申请号：US15156327

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Na Choi ,  Young-Deuk Kim ,  Jae-Choon Kim ,  Eon-Soo Jang ,  Hee-Jung Hwang

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/45099

Abstract: A package substrate may include an insulating substrate, internal circuits and a warpage-suppressing member. The insulating substrate may have a plurality of mount regions in which semiconductor chips may be mounted, and a peripheral region. The internal circuits may be arranged in the mount regions. The warpage-suppressing member is different from the semiconductor chips and may be arranged in at least one of the mount regions to suppress a warpage of the insulating substrate. Thus, warpage of the package substrate may be suppressed during a reflow process.