Address aligner and memory device including the same

    公开(公告)号:US09601172B2

    公开(公告)日:2017-03-21

    申请号:US14668232

    申请日:2015-03-25

    CPC classification number: G11C8/18 G11C8/06

    Abstract: An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal.

    Air conditioner controlling system and air conditioner controlling method

    公开(公告)号:US11060749B2

    公开(公告)日:2021-07-13

    申请号:US16063676

    申请日:2016-12-07

    Abstract: The present disclosure relates to an air conditioner, an air conditioner controlling system, and an air conditioner controlling method. The air conditioner controlling system includes one or more controlled air conditioners, a main controlling air conditioner having control authority over, from among the one or more controlled air conditioners, one or more controlled air conditioners that belong to an upper rank group corresponding to the main controlling air conditioner, and a sub-controlling air conditioner having control authority over, from among the one or more controlled air conditioners, one or more controlled air conditioners that belong to a first lower rank group.

    Data output circuit, memory device including the data output circuit, and operating method of the memory device

    公开(公告)号:US10559334B2

    公开(公告)日:2020-02-11

    申请号:US16031408

    申请日:2018-07-10

    Abstract: A memory device includes a memory cell array storing input data, a clock generator circuit generating first clocks and second clocks using a reference clock, a phase information generator circuit comparing a phase of the reference clock and a phase of at least one of the first clocks and the second clocks and generating phase information as a comparison result, an intermediate data generator circuit serializing a part of input data provided from the memory cell array based on the first clocks to generate first data, serializing a remaining part of the input data to generate second data, and selectively swapping the first data and the second data using the phase information to generate intermediate data, and an output data generator circuit serializing the intermediate data using the second clocks, to output output data through one output data line.

Patent Agency Ranking