公开(公告)号：US11106535B2

公开(公告)日：2021-08-31

申请号：US16926000

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kijun Lee ,  Yeonggeol Song ,  Sungrae Kim ,  Chanki Kim ,  Myungkyu Lee ,  Sanguhn Cha

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/00

Abstract: An error correction circuit includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page. The ECC decoder reads the codeword from the target page as a read codeword based on an externally provided address to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.

公开(公告)号：US20210194508A1

公开(公告)日：2021-06-24

申请号：US16987554

申请日：2020-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G06F9/30

Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

公开(公告)号：US20210191810A1

公开(公告)日：2021-06-24

申请号：US16934677

申请日：2020-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Chanki Kim ,  Kijun Lee ,  Sanguhn Cha ,  Myungkyu Lee

IPC: G06F11/10 ,  H03M13/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.

公开(公告)号：US11681458B2

公开(公告)日：2023-06-20

申请号：US17090726

申请日：2020-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kijun Lee ,  Sung-Rae Kim ,  Chanki Kim ,  Yeonggeol Song ,  Yesin Ryu ,  Jaeyoun Youn ,  Myungkyu Lee

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1048 ,  G11C29/52

Abstract: A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

公开(公告)号：US11463110B2

公开(公告)日：2022-10-04

申请号：US16987554

申请日：2020-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

IPC: H03M13/00 ,  H03M13/15 ,  G06F9/30 ,  G06F11/10 ,  H03M13/11

Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

公开(公告)号：US11416335B2

公开(公告)日：2022-08-16

申请号：US16934677

申请日：2020-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunghye Cho ,  Chanki Kim ,  Kijun Lee ,  Sanguhn Cha ,  Myungkyu Lee

IPC: G06F11/10 ,  H03M13/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array is coupled to word-line and bit-lines and is divided into sub array blocks. The error correction circuit generates parity data based on main data using an error correction code (ECC). The control logic circuit controls the error correction circuit and the I/O gating circuit based on a command and address. The control logic circuit stores the main data and the parity data in (k+1) target sub array blocks in the second direction among the sub array blocks, and controls the I/O gating circuit such that a portion of the (k+1) target sub array blocks store both of a portion of the main data and a portion of the parity data.

公开(公告)号：US11088710B2

公开(公告)日：2021-08-10

申请号：US16809949

申请日：2020-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun Lee ,  Chanki Kim ,  Sunghye Cho ,  Myungkyu Lee

IPC: H03M13/15 ,  H03M13/11 ,  G06F17/16

Abstract: A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.