公开(公告)号：US20240274172A1

公开(公告)日：2024-08-15

申请号：US18133247

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-YEON SHIN ,  DAEHOON NA ,  JONGHWA KIM

IPC: G11C7/22 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC classification number: G11C7/22 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.

公开(公告)号：US20220139432A1

公开(公告)日：2022-05-05

申请号：US17243870

申请日：2021-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-YEON SHIN ,  DAEHOON NA ,  JONGHWA KIM

IPC: G11C7/22 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.

公开(公告)号：US20240072773A1

公开(公告)日：2024-02-29

申请号：US18331223

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAEHOON NA ,  SEONKYOO LEE ,  SEUNGJUN BAE ,  TAESUNG LEE

IPC: H03K3/013 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  H03K3/017

CPC classification number: H03K3/013 ,  G06F13/1668 ,  G11C7/1093 ,  G11C7/222 ,  H03K3/017 ,  G06F2213/16

Abstract: An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.