公开(公告)号：US20170257233A1

公开(公告)日：2017-09-07

申请号：US15425609

申请日：2017-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUKJUN SUNG ,  HYUNJAE KANG ,  DOHYUNG KIM ,  JAEHUN CHOI

IPC: H04L25/03 ,  H04L5/00 ,  H04L29/06

CPC classification number: H04L25/03273 ,  H04L5/0048 ,  H04L7/033 ,  H04L7/042 ,  H04L25/03853 ,  H04L69/22

Abstract: An electronic device includes a clock recovery circuit, a converter circuit, and a decoder circuit. The clock recovery circuit generates a reference clock. The converter circuit generates a conversion value that corresponds to a difference between a phase of reception data and a phase of the reference clock. The decoder circuit analyzes a reception characteristic of an antenna based on conversion values that corresponds to a start-of-frame (SOF) marker. The decoder circuit decodes a conversion value that corresponds to encoded data following the SOF marker in the reception data, with reference to the analyzed reception characteristic, into a digital value.

公开(公告)号：US20220070999A1

公开(公告)日：2022-03-03

申请号：US17356940

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： DONGYOON SEO ,  SANGKEUN KWAK ,  DOHYUNG KIM ,  KYEONGSEON PARK ,  HWANWOOK PARK ,  WONSEOP LEE ,  DAAE HEO

IPC: H05K1/02 ,  H05K1/14

Abstract: A memory module including: a first printed circuit board; a first socket and a second socket; and a daisy chain pattern formed in a first region of the first printed circuit board and connected to the first socket and the second socket, wherein an electrical signal on the daisy chain pattern is transferred to a host device when the first socket and the second socket are connected to the host device.

公开(公告)号：US20160099155A1

公开(公告)日：2016-04-07

申请号：US14840114

申请日：2015-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEJUN PARK ,  DOHYUNG KIM ,  JAIHYUNG WON ,  SANGHO ROH ,  EUNSOL SHIN ,  SEUNG MOO LEE ,  GYUWAN CHOI

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  C23C16/50 ,  C23C16/26 ,  C23C14/06 ,  C23C16/30 ,  C23C14/22 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3081 ,  C23C16/26 ,  C23C16/56 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10888 ,  H01L29/4236

Abstract: A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N2O). A source of carbon and the nitrous oxide (N2O) are introduced to the substrate under a plasma ambient of an inert gas. The amorphous carbon layer has a nitrogen content ranging from about 0.05 at % to about 30 at % and an oxygen content ranging from about 0.05 at % to about 10 at %. In forming a semiconductor device, the hard mask layer is patterned, and a target layer beneath the hard mask layer is etched using the patterned hard mask layer as an etch mask.

Abstract translation: 在基板上形成硬掩模层的方法包括使用一氧化二氮（N2O）形成无定形碳层。 在惰性气体的等离子体环境下将碳源和一氧化二氮（N 2 O）源引入衬底。 无定形碳层的氮含量范围为约0.05at％至约30at％，氧含量为约0.05at％至约10at％。 在形成半导体器件时，硬掩模层被图案化，并且使用图案化的硬掩模层作为蚀刻掩模来蚀刻硬掩模层下面的目标层。

公开(公告)号：US20250102926A1

公开(公告)日：2025-03-27

申请号：US18618345

申请日：2024-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghwan LEE ,  DOHYUNG KIM ,  JINHONG PARK ,  Sungbin JEON

IPC: G03F7/00

Abstract: Disclosed are a reticle masking device, a substrate processing apparatus, and a substrate processing method. The reticle masking device comprises a first masking device that provides a mask hole, a second masking device that is movable in a first direction with respect to the first masking device, and an optical sensor device coupled to the second masking device. The second masking device provides a slit vertically penetrates the second masking device and that overlaps the mask hole. The optical sensor device includes a first sensor fixedly coupled to a bottom surface of the second masking device, and a second sensor that stands opposite to the first sensor across the slit and is fixedly coupled to the bottom surface of the second masking device.

公开(公告)号：US20240074058A1

公开(公告)日：2024-02-29

申请号：US18164748

申请日：2023-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAEKWANG LEE ,  HYUN A LEE ,  DOHYUNG KIM ,  DONGMIN JANG ,  JINWOO JANG

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/28

CPC classification number: H05K1/117 ,  H05K3/18 ,  H05K3/28 ,  H05K1/09 ,  H05K2201/032 ,  H05K2201/0347 ,  H05K2201/09381 ,  H05K2201/099

Abstract: A module board includes a substrate having a wire pattern on a surface, a protection layer covering the surface of the substrate so as to expose one edge region of the substrate surface, and a plurality of tab terminals connected to the wire pattern and arranged on one edge region. Each tab terminal has a width larger than a width of the wire pattern. Each tab terminal has a pattern layer. A protection layer is on the pattern layer at a region where each tab terminal is connected to the wire pattern, and a plating layer is on a remainder of the pattern layer.