公开(公告)号：US20190157294A1

公开(公告)日：2019-05-23

申请号：US16118647

申请日：2018-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Young-Hwan SON ,  Byung-Kwan YOU ,  Eun-Taek JUNG

IPC: H01L27/11582 ,  H01L21/768 ,  H01L23/532 ,  H01L21/56 ,  H01L21/764 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/565 ,  H01L21/764 ,  H01L21/76832 ,  H01L23/5329 ,  H01L27/1157 ,  H01L28/88 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833

Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.

公开(公告)号：US20240172441A1

公开(公告)日：2024-05-23

申请号：US18419818

申请日：2024-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Taek JUNG ,  JOONG-SHIK SHIN ,  BYUNG-KWAN YOU

IPC: H10B43/27 ,  H01L21/311 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/31111 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/27 ,  H10B43/35

Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.

公开(公告)号：US20210005628A1

公开(公告)日：2021-01-07

申请号：US16933328

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Taek JUNG ,  Joong-Shik SHIN ,  Byung-Kwan YOU

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/311 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157

Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.