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公开(公告)号：US20140377926A1
公开(公告)日：2014-12-25
申请号：US14294287
申请日：2014-06-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae-Gon KIM , Jong-Hoon Kang , Eun-Young Jo , Gil-Heyun Choi , Han-Mei Choi
IPC: H01L21/225 , H01L29/66
CPC classification number: H01L29/66795 , H01L21/2252 , H01L29/66803 , H01L29/785
Abstract: A fin type active pattern is formed on a substrate. The fin type active pattern projects from the substrate. A diffusion film is formed on the fin type active pattern. The diffusion film includes an impurity. The impurity is diffused into a lower portion of the fin type active pattern to form a punch-through stopper diffusion layer.
Abstract translation: 在基板上形成翅片型有源图案。 翅片型有源图案从基板突出。 扩散膜形成在翅片型活性图案上。 扩散膜包括杂质。 杂质扩散到翅片型有源图案的下部，形成穿通止动器扩散层。
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公开(公告)号：US09236259B2
公开(公告)日：2016-01-12
申请号：US14276213
申请日：2014-05-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-Young Jo , Jong-Hoon Kang , Tae-Gon Kim , Han-Mei Choi
IPC: H01L21/28 , H01L21/225 , H01L21/8238 , H01L29/66
CPC classification number: H01L21/28035 , H01L21/2255 , H01L21/28061 , H01L21/823842 , H01L29/66575
Abstract: A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.
Abstract translation: 可以提供制造具有掺杂层的半导体器件的方法。 该方法包括提供具有第一区域和第二区域的衬底，在衬底上形成栅极电介质层，在栅极电介质层上形成第一栅电极层，在第一栅电极层上形成第一掺杂层，形成第 在所述第一掺杂层上形成第一覆盖层，在所述第一区域中的所述第一覆盖层上形成掩模图案，所述掩模图案在所述第二区域中暴露所述第一覆盖层，在所述第二区域中去除所述第一覆盖层和所述第一掺杂层 去除所述掩模图案，以及在所述第一区域中的所述第一覆盖层和所述第二区域中的所述第一栅极电极层上形成第二掺杂层。
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公开(公告)号：US08883608B2
公开(公告)日：2014-11-11
申请号：US13894736
申请日：2013-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Hoon Kang , Tae-Gon Kim , Han-Mei Choi , Eun-Young Jo
IPC: H01L21/76 , H01L27/108 , H01L21/3213 , H01L23/544 , H01L49/02 , H01L21/027
CPC classification number: H01L21/027 , H01L21/32139 , H01L23/544 , H01L27/10852 , H01L27/10894 , H01L28/91 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
Abstract: An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening.
Abstract translation: 在包括第一区域和第二区域的基板上形成对准标记。 对准标记形成在第二区域中。 在对准标记和基板上形成包含结晶材料的蚀刻目标层。 第一区域中的蚀刻目标层是部分非晶化的。 蚀刻非晶化蚀刻目标层以形成开口。
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公开(公告)号：US20140065793A1
公开(公告)日：2014-03-06
申请号：US13894736
申请日：2013-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Hoon Kang , Tae-Gon Kim , Han-Mei Choi , Eun-Young Jo
IPC: H01L21/027
CPC classification number: H01L21/027 , H01L21/32139 , H01L23/544 , H01L27/10852 , H01L27/10894 , H01L28/91 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
Abstract: An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening.
Abstract translation: 在包括第一区域和第二区域的基板上形成对准标记。 对准标记形成在第二区域中。 在对准标记和基板上形成包含结晶材料的蚀刻目标层。 第一区域中的蚀刻目标层是部分非晶化的。 蚀刻非晶化蚀刻目标层以形成开口。
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