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    Methods of manufacturing a semiconductor device
    1.
    发明授权
    Methods of manufacturing a semiconductor device 有权

    公开(公告)号：US10593557B2

    公开(公告)日：2020-03-17

    申请号：US16123262

    申请日：2018-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-In Choi ,  Sang-Hoon Han ,  Sun-Jung Kim ,  Tae-Gon Kim ,  Hyun-Chul Song

    IPC: H01L21/4763 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/78

    Abstract: A method of manufacturing a semiconductor device, the method including forming dummy gate structures on a substrate; forming spacers on sidewalls of the dummy gate structures; forming a preliminary first interlayer insulation pattern to fill a gap between adjacent spacers; etching an upper portion of the preliminary first interlayer insulation pattern through a first etching process to form a preliminary second interlayer insulation pattern; implanting an ion on the dummy gate structures, the spacers, and the preliminary second interlayer insulation pattern through an ion-implanting process; etching an upper portion of the preliminary second interlayer insulation pattern through a second etching process to form an interlayer insulation pattern having a flat upper surface; and forming a capping pattern on the interlayer insulation pattern to fill a gap between the spacers.

    Etching apparatus and etching method
    2.
    发明授权
    Etching apparatus and etching method 有权
    蚀刻装置和蚀刻方法

    公开(公告)号：US09105452B2

    公开(公告)日：2015-08-11

    申请号：US14199160

    申请日：2014-03-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyung-Yub Jeon ,  Jeong-Yun Lee ,  Kyung-Sun Kim ,  Tae-Gon Kim

    IPC: H01L21/00 ,  H01J37/32

    CPC classification number: H01J37/32568 ,  H01J37/32577 ,  H01J37/32706 ,  H01J37/32715

    Abstract: An apparatus for an etching process includes a chamber, a plasma generator disposed in the chamber, a stacked structure disposed in the chamber to support a substrate thereon and including an electrode plate and an insulation coating layer on the electrode plate, electrode rods inserted into through holes of the stacked structure to penetrate through the stacked structure, directly contacting the substrate and spaced apart from sidewalls of the through holes of the stacked structure, at least one DC pulse generator generating a DC pulse to the electrode plate and the electrode rods, first connection lines connecting the DC pulse generator to the electrode rods, and at least one second connection line connecting the DC pulse generator to a lower portion of the electrode plate.

    Abstract translation: 一种用于蚀刻工艺的设备包括：室，设置在室中的等离子体发生器，堆叠结构，设置在室中以在其上支撑基板，并且在电极板上包括电极板和绝缘涂层，电极棒插入 层叠结构的孔穿透堆叠结构，直接接触基板并与堆叠结构的通孔的侧壁间隔开，至少一个DC脉冲发生器首先向电极板和电极棒产生DC脉冲 将DC脉冲发生器连接到电极棒的连接线以及将DC脉冲发生器连接到电极板的下部的至少一个第二连接线。

    Method of manufacturing semiconductor device having doped layer
    4.
    发明授权
    Method of manufacturing semiconductor device having doped layer 有权
    制造具有掺杂层的半导体器件的方法

    公开(公告)号：US09236259B2

    公开(公告)日：2016-01-12

    申请号：US14276213

    申请日：2014-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun-Young Jo ,  Jong-Hoon Kang ,  Tae-Gon Kim ,  Han-Mei Choi

    IPC: H01L21/28 ,  H01L21/225 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L21/28035 ,  H01L21/2255 ,  H01L21/28061 ,  H01L21/823842 ,  H01L29/66575

    Abstract: A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.

    Abstract translation: 可以提供制造具有掺杂层的半导体器件的方法。 该方法包括提供具有第一区域和第二区域的衬底，在衬底上形成栅极电介质层，在栅极电介质层上形成第一栅电极层，在第一栅电极层上形成第一掺杂层，形成第 在所述第一掺杂层上形成第一覆盖层，在所述第一区域中的所述第一覆盖层上形成掩模图案，所述掩模图案在所述第二区域中暴露所述第一覆盖层，在所述第二区域中去除所述第一覆盖层和所述第一掺杂层 去除所述掩模图案，以及在所述第一区域中的所述第一覆盖层和所述第二区域中的所述第一栅极电极层上形成第二掺杂层。

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