公开(公告)号：US12009342B2

公开(公告)日：2024-06-11

申请号：US17383608

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoon Kim ,  Sunwon Kang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265

Abstract: A semiconductor package includes a substrate, first and second semiconductor chip structures on the substrate and spaced apart from each other in a first horizontal direction, a mold layer on the substrate and covering both the first and second semiconductor chip structures, and a supporting structure on the mold layer and distal from the upper surface of the substrate than both the first and second semiconductor chip structures in a vertical direction. The supporting structure includes first and second supporting portions, spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction and the vertical direction. Each of the first and second supporting portions has a bar shape or a linear shape extending in the first horizontal direction. At least one of the first supporting portion or the second supporting portion overlaps the first and second semiconductor chips in the vertical direction.

公开(公告)号：US20220077110A1

公开(公告)日：2022-03-10

申请号：US17383608

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoon Kim ,  Sunwon Kang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, first and second semiconductor chip structures on the substrate and spaced apart from each other in a first horizontal direction, a mold layer on the substrate and covering both the first and second semiconductor chip structures, and a supporting structure on the mold layer and distal from the upper surface of the substrate than both the first and second semiconductor chip structures in a vertical direction. The supporting structure includes first and second supporting portions, spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction and the vertical direction. Each of the first and second supporting portions has a bar shape or a linear shape extending in the first horizontal direction. At least one of the first supporting portion or the second supporting portion overlaps the first and second semiconductor chips in the vertical direction.

公开(公告)号：US11538142B2

公开(公告)日：2022-12-27

申请号：US16835995

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongchul Bak ,  Keunhwi Koo ,  Hyoungjoon Kim ,  Joonyoung Chang ,  Kilhyung Cha

IPC: G06K9/54 ,  G06T5/50 ,  G06T7/223 ,  G06T1/00 ,  G06T1/20 ,  G06T1/60

Abstract: An image signal processor, an operating method thereof, and an image processing system are provided. The image processing system includes: a control processor configured to generate and output setting information corresponding to N (where N is an integer of 2 or more) image frames; and an image signal processor configured to perform image processing on the N image frames received from an image sensor based on the setting information, and generate an interrupt signal and transmit the interrupt signal to the control processor based on completion of the image processing performed on the N image frame.

公开(公告)号：US20170141092A1

公开(公告)日：2017-05-18

申请号：US15254259

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoon Kim ,  Kwangil PARK ,  Seok-Hong KWON ,  Chulsung PARK ,  Eunsung SEO ,  Heejin LEE ,  Kijong PARK

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.

公开(公告)号：US20240266276A1

公开(公告)日：2024-08-08

申请号：US18474336

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinmo Kwon ,  Jitaek Oh ,  Hyoungjoon Kim

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A strip substrate comprises a dielectric layer comprising a unit region and a saw line region, a saw line pattern on the saw line region, a conductive dummy pattern extending from the saw line pattern and toward the unit region, and power/ground patterns on the unit region. The power/ground pattern includes a first lateral surface that extends in a first direction and is proximate to the saw line pattern, a second lateral surface that extends in a second direction and is proximate to the conductive dummy pattern, and a third lateral surface that connects the first lateral surface and the second lateral surface.

公开(公告)号：US09899361B2

公开(公告)日：2018-02-20

申请号：US15254259

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoungjoon Kim ,  Kwangil Park ,  Seok-Hong Kwon ,  Chulsung Park ,  Eunsung Seo ,  Heejin Lee ,  Kijong Park

IPC: H01L23/02 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.