公开(公告)号：US20250029941A1

公开(公告)日：2025-01-23

申请号：US18439381

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSU HWANG ,  UN-BYOUNG KANG ,  KUYOUNG KIM ,  JUMYONG PARK ,  DONGJOON OH ,  SANGHOO CHO

IPC: H01L23/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a substrate, a seed layer on the substrate, and a wiring pad on the seed layer. The wiring pad includes a pad portion, and a capping layer on the seed layer and covering a top surface and a lateral surface of the pad portion. A bottom surface of the pad portion is in contact with a top surface of the seed layer. A width of the top surface of the pad portion is greater than a width of the bottom surface of the pad portion.

公开(公告)号：US20250125290A1

公开(公告)日：2025-04-17

申请号：US18647497

申请日：2024-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSU HWANG ,  JUMYONG PARK ,  DONGJOON OH ,  SANGHOO CHO ,  JEONGGI JIN

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a structure including a dielectric layer and a wire pattern embedded in the dielectric layer. The dielectric layer includes first regions and a second region around the first regions. The second region has an upper surface positioned at a lower level than upper surfaces of the first regions. A barrier layer is on the structure. The barrier layer is disposed on each first region among the first regions and is connected to the wire pattern. A seed metal layer is on the barrier layer. A conductive pad is on the seed metal layer.

公开(公告)号：US20240006288A1

公开(公告)日：2024-01-04

申请号：US18369684

申请日：2023-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  JUMYONG PARK ,  JIN HO AN ,  Dongjoon Oh ,  JEONGGI JIN ,  HYUNSU HWANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L23/49816 ,  H01L2225/1058 ,  H01L2224/16235 ,  H01L2924/182 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US20230096678A1

公开(公告)日：2023-03-30

申请号：US17850714

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNYUN KWEON ,  JUMYONG PARK ,  SOLJI SONG ,  DONGJOON OH ,  CHUNGSUN LEE ,  HYUNSU HWANG

IPC: H01L21/78 ,  H01L21/02

Abstract: A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

公开(公告)号：US20230010936A1

公开(公告)日：2023-01-12

申请号：US17568355

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONGGI JIN ,  GYUHO KANG ,  UNBYOUNG KANG ,  HEEWON KIM ,  JUMYONG PARK ,  HYUNSU HWANG

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.