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    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20230132272A1

    公开(公告)日：2023-04-27

    申请号：US17870898

    申请日：2022-07-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUN YOUNG OH ,  UN-BYOUNG KANG ,  BYEONGCHAN KIM ,  JUMYONG PARK ,  CHUNGSUN LEE

    IPC: H01L23/00 ,  H01L25/065

    Abstract: The semiconductor device may include a substrate, a first insulating layer on a bottom surface of the substrate, an interconnection structure in the first insulating layer, a second insulating layer on a bottom surface of the first insulating layer, and a plurality of lower pads provided in the second insulating layer. Each lower pad may be provided such a width of a top surface thereof is smaller than a width of a bottom surface thereof. The lower pads may include first, second, and third lower pads. In a plan view, the first and third lower pads may be adjacent to center and edge portions of the substrate, respectively, and the second lower pad may be disposed therebetween. A width of a bottom surface of the second lower pad may be smaller than that of the first lower pad and may be larger than that of the third lower pad.

    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE
    5.
    发明公开
    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE 审中-公开

    公开(公告)号：US20230290718A1

    公开(公告)日：2023-09-14

    申请号：US18199824

    申请日：2023-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

    CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/49816

    Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE
    6.
    发明申请
    INTERCONNECTION STRUCTURE, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR PACKAGE INCLUDING INTERCONNECTION STRUCTURE 有权

    公开(公告)号：US20220068785A1

    公开(公告)日：2022-03-03

    申请号：US17324569

    申请日：2021-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JI-SEOK HONG ,  DONGWOO KIM ,  HYUNAH KIM ,  UN-BYOUNG KANG ,  CHUNGSUN LEE

    IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

    Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same. The interconnection structure comprises a first dielectric layer, a wiring pattern formed in the first dielectric layer, a portion of the wiring pattern exposed with respect to a top surface of the first dielectric layer, a second dielectric layer on the first dielectric layer, the second dielectric layer including an opening that exposes the exposed portion of the wiring pattern, a pad formed in the opening of the second dielectric layer, the pad including a base part that covers the exposed portion of the wiring pattern at a bottom of the opening and a sidewall part that extends upwardly along an inner lateral surface of the opening from the base part, a first seed layer interposed between the second dielectric layer and a first lateral surface of the sidewall part, the first seed layer being in contact with the first lateral surface and the second dielectric layer, and a second seed layer that conformally covers a second lateral surface of the sidewall part and a top surface of the base part, the second lateral surface being opposite to the first lateral surface the second dielectric layer.

    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
    10.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230096678A1

    公开(公告)日：2023-03-30

    申请号：US17850714

    申请日：2022-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JUNYUN KWEON ,  JUMYONG PARK ,  SOLJI SONG ,  DONGJOON OH ,  CHUNGSUN LEE ,  HYUNSU HWANG

    IPC: H01L21/78 ,  H01L21/02

    Abstract: A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

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