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    METHODS OF FORMING PATTERNS OF A SEMICONDUCTOR DEVICES
    4.
    发明申请
    METHODS OF FORMING PATTERNS OF A SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20170103891A1

    公开(公告)日：2017-04-13

    申请号：US15223710

    申请日：2016-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Sub LEE ,  Kyoung-Ha Eom ,  Ha-Neul Lee ,  Sang-Gyo Chung

    IPC: H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/0337 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11582 ,  H01L28/00

    Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.

    Methods of forming patterns of a semiconductor devices
    6.
    发明授权
    Methods of forming patterns of a semiconductor devices 有权

    公开(公告)号：US09837273B2

    公开(公告)日：2017-12-05

    申请号：US15223710

    申请日：2016-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jong-Sub Lee ,  Kyoung-Ha Eom ,  Ha-Neul Lee ,  Sang-Gyo Chung

    IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/108

    CPC classification number: H01L21/0337 ,  H01L21/32139 ,  H01L27/10844 ,  H01L27/11582 ,  H01L28/00

    Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.

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