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1.发明授权公开(公告)号：US10203909B2
公开(公告)日：2019-02-12
申请号：US15421514
申请日：2017-02-01
发明人： Youngkwang Yoo , Youngjin Cho , Han-Ju Lee , JinHyeok Choi
IPC分类号： G06F3/06 , G11C8/12 , G06F12/0868
摘要： A nonvolatile memory module may include a nonvolatile memory device, a nonvolatile memory controller configured to control the nonvolatile memory device, a volatile memory device configured as a cache memory of the nonvolatile memory device, and a module controller configured to receive a command and an address from an external device, external to the nonvolatile memory module, and to send a volatile memory command and a volatile memory address to the volatile memory device through a first bus and a nonvolatile memory command and a nonvolatile memory address to the controller through a second bus in response to the received command and address. The volatile memory device is configured to load two or more cache data on each of two or more memory data line groups and two or more tags on each of two or more tag data line groups in response to the volatile memory address.
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2.发明授权公开(公告)号：US09542264B2
公开(公告)日：2017-01-10
申请号：US14541303
申请日：2014-11-14
发明人： Kwangseok Im , Jung-Yeon Yoon , Han-Ju Lee , Ha-Neul Jeong
CPC分类号： G06F11/1004 , G06F11/1008 , G06F11/1076 , H03M13/09
摘要： A memory controller comprises at least one interface configured to receive a request, user data, and an address from an external source, a first data check engine configured to generate data check information based on the received address and the user data in response to the received request, and a second data check engine configured to check the integrity of the user data based on the generated data check information where the user data is transmitted to the nonvolatile memory. The memory controller is configured to transmit the user data received from the external source to an external destination where the integrity of the user data is verified according to a check result, and is further configured to transmit an interrupt signal to the external source and the external destination where the check result indicates that the user data comprises an error.
摘要翻译： 存储器控制器包括被配置为从外部源接收请求，用户数据和地址的至少一个接口，第一数据检查引擎，被配置为基于接收到的地址和用户数据响应于所接收的地址生成数据检查信息 以及第二数据检查引擎，被配置为基于将用户数据发送到非易失性存储器的所生成的数据检查信息来检查用户数据的完整性。 存储器控制器被配置为根据检查结果将从外部源接收的用户数据发送到外部目的地，其中用户数据的完整性被验证，并且还被配置为将中断信号发送到外部源和外部 检查结果指示用户数据包含错误的目的地。
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公开(公告)号：US10949094B2
公开(公告)日：2021-03-16
申请号：US16298318
申请日：2019-03-11
发明人： Han-Ju Lee , Youngkwang Yoo , Youngjin Cho
摘要： A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.
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公开(公告)号：US10261697B2
公开(公告)日：2019-04-16
申请号：US15055689
申请日：2016-02-29
发明人： Han-Ju Lee , Youngkwang Yoo , Youngjin Cho
IPC分类号： G06F3/06
摘要： A storage device includes a data buffer, a device controller, and nonvolatile memories. The data buffer is configured to transact data from an external device. The device controller is configured to receive a command and an address from an external device, to control the data buffers, and to transact data with the data buffers. The nonvolatile memories are configured to perform write, read, and erase operations under control of the device controller. When a first link training between an external device and the data buffers is performed by the external device, the device controller performs a second link training between the device controller and a data buffer internally without control of the external device.
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公开(公告)号：US10152413B2
公开(公告)日：2018-12-11
申请号：US15083425
申请日：2016-03-29
发明人： Han-Ju Lee , Youngjin Cho , Sungyong Seo , Youngkwang Yoo
摘要： The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.
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公开(公告)号：US11216394B2
公开(公告)日：2022-01-04
申请号：US16411330
申请日：2019-05-14
发明人： Han-Ju Lee , Youngkwang Yoo , Youngjin Cho
摘要： A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.
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公开(公告)号：US10324869B2
公开(公告)日：2019-06-18
申请号：US15260916
申请日：2016-09-09
发明人： Han-Ju Lee , Youngkwang Yoo , Youngjin Cho
摘要： A storage device includes random access memories, nonvolatile memory devices, a controller configured to control the nonvolatile memory devices, and a driver circuit configured to receive a command and an address from an external device, output a buffer command according to the command and the address, and transmit the command and the address to one of a first channel connected to the random access devices and a second channel connected to the controller according to the command and the address. The storage device further includes a plurality of data buffers configured to communicate with the external device and electrically connect the external device to one of a third channel connected to the random access memory devices and a fourth channel connected to the controller in response to the buffer command. Each of the data buffers includes a FIFO (first-in first-out) circuit.
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公开(公告)号：US20160357462A1
公开(公告)日：2016-12-08
申请号：US15096877
申请日：2016-04-12
发明人： Hee Hyun Nam , Jaegeun Park , Sungyong Seo , Youngkwang Yoo , Han-Ju Lee , Youngjin Cho
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0613 , G06F3/0616 , G06F3/0656 , G06F3/0659 , G06F3/068 , G06F3/0685
摘要： Disclosed is a nonvolatile memory module. The nonvolatile memory module includes at least one nonvolatile memory, a random access memory (RAM) and a device controller. Responsive to receiving a write request comprising sub-data from a host, the device controller accumulates the sub-data in the RAM and programs the accumulated sub-data in the nonvolatile memory. A size of the sub-data is smaller than a size of a default transmission unit provided from the host.
摘要翻译： 公开了一种非易失性存储器模块。 非易失性存储器模块包括至少一个非易失性存储器，随机存取存储器（RAM）和器件控制器。 响应于从主机接收到包含子数据的写入请求，设备控制器将该子数据累加在RAM中，并将累积的子数据编程在非易失性存储器中。 子数据的大小小于从主机提供的默认传输单元的大小。
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公开(公告)号：US11868270B2
公开(公告)日：2024-01-09
申请号：US17820631
申请日：2022-08-18
发明人： Seung Moon Woo , Seon Bong Kim , Han-Ju Lee
IPC分类号： G06F12/1045 , G06F12/0862 , G06F12/1081
CPC分类号： G06F12/1045 , G06F12/0862 , G06F12/1081
摘要： A storage device includes a storage controller and a host interface which sends an address translation service request to a host. The host interface includes an address translation cache which stores first address information included in the address translation service request, and an address translation service latency storage which stores latency-related information including a first time until the address translation cache receives an address translation service response corresponding to the address translation service request from the host. After the host interface sends the address translation service request to the host based on the latency-related information including the first time, and after the first time elapses, the storage controller polls the host interface.
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公开(公告)号：US10649894B2
公开(公告)日：2020-05-12
申请号：US16195533
申请日：2018-11-19
发明人： Han-Ju Lee , Youngjin Cho , Sungyong Seo , Youngkwang Yoo
摘要： The nonvolatile memory module includes at least one nonvolatile memory device and a device controller configured to receive a storage command from an external device and to perform an operation corresponding to the received storage command. The device controller includes a random access memory (RAM). After completing the corresponding operation, the device controller stores status information in the RAM and then transmits an alert signal to the external device.
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