公开(公告)号：US20160020301A1

公开(公告)日：2016-01-21

申请号：US14707144

申请日：2015-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Bum Park ,  Dong Chan Suh ,  Kwan Heum Lee

IPC: H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a method of manufacturing a semiconductor device including: forming a gate electrode structure on an active region of a semiconductor substrate; forming recesses in regions positioned on both sides of the gate electrode structure on the active region; performing a pre-treatment on the recesses using an inert gas plasma; growing epitaxial layers for a source and a drain on the pre-treated recesses; and forming a source electrode structure and a drain electrode structure in the epitaxial layers for the source and the drain, respectively. Also provided is a method in which, after an etching process for forming recesses and/or after an etching process for forming a contact hole, an etched surface may be treated with an inert gas plasma before growing an epitaxial layer. Thus, one or two types of plasma treatment may be employed in the method.

Abstract translation: 提供一种制造半导体器件的方法，包括：在半导体衬底的有源区上形成栅电极结构; 在所述有源区上形成位于所述栅电极结构两侧的区域中的凹槽; 使用惰性气体等离子体对凹部进行预处理; 在预处理的凹槽上生长用于源极和漏极的外延层; 以及在源极和漏极的外延层中分别形成源极结构和漏极结构。 还提供了一种方法，其中在用于形成凹陷的蚀刻工艺和/或用于形成接触孔的蚀刻工艺之后，可以在生长外延层之前用惰性气体等离子体处理蚀刻表面。 因此，在该方法中可以采用一种或两种类型的等离子体处理。

公开(公告)号：US09502532B2

公开(公告)日：2016-11-22

申请号：US14707144

申请日：2015-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong Bum Park ,  Dong Chan Suh ,  Kwan Heum Lee

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a method of manufacturing a semiconductor device including: forming a gate electrode structure on an active region of a semiconductor substrate; forming recesses in regions positioned on both sides of the gate electrode structure on the active region; performing a pre-treatment on the recesses using an inert gas plasma; growing epitaxial layers for a source and a drain on the pre-treated recesses; and forming a source electrode structure and a drain electrode structure in the epitaxial layers for the source and the drain, respectively. Also provided is a method in which, after an etching process for forming recesses and/or after an etching process for forming a contact hole, an etched surface may be treated with an inert gas plasma before growing an epitaxial layer. Thus, one or two types of plasma treatment may be employed in the method.

Abstract translation: 提供一种制造半导体器件的方法，包括：在半导体衬底的有源区上形成栅电极结构; 在所述有源区上形成位于所述栅电极结构两侧的区域中的凹槽; 使用惰性气体等离子体对凹部进行预处理; 在预处理的凹槽上生长用于源极和漏极的外延层; 以及在源极和漏极的外延层中分别形成源极结构和漏极结构。 还提供了一种方法，其中在用于形成凹陷的蚀刻工艺和/或用于形成接触孔的蚀刻工艺之后，可以在生长外延层之前用惰性气体等离子体处理蚀刻表面。 因此，在该方法中可以采用一种或两种类型的等离子体处理。

公开(公告)号：US20170330905A1

公开(公告)日：2017-11-16

申请号：US15397065

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Suk Tak ,  Hong Bum Park ,  Won Oh Seo ,  Guk Hyon Yon ,  Ju Ri Lee

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/14621 ,  H01L27/14627

Abstract: A pixel array may include an array of microlenses, an array of photodetectors, and an array of color filters. The array of microlenses concentrate incoming light through respective filters in the array of color filters to respective photodetectors in the array of photodetectors. An anti-reflective layer is included between the photodetectors and color filters. The anti-reflective layer includes a first layer having a first index of refraction, a second layer closer to the color filter than the first layer having a second, higher, index of refraction, and a lattice adjusting layer between the first and second layers. The second layer includes a rutile phase TiO2 layer and the lattice adjusting layer includes a crystalline material having a lattice constant similar to that of the rutile phase TiO2 layer.

公开(公告)号：US10056491B2

公开(公告)日：2018-08-21

申请号：US15420512

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Hoon Jeong ,  Hong Bum Park ,  HanMei Choi ,  Jae Young Park ,  Seung Hyun Lim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/41 ,  H01L27/08 ,  H01L27/10 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/28158 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.