公开(公告)号：US10056491B2

公开(公告)日：2018-08-21

申请号：US15420512

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Hoon Jeong ,  Hong Bum Park ,  HanMei Choi ,  Jae Young Park ,  Seung Hyun Lim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/41 ,  H01L27/08 ,  H01L27/10 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/7854 ,  H01L21/28158 ,  H01L21/823431 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.

公开(公告)号：US10020318B2

公开(公告)日：2018-07-10

申请号：US15218610

申请日：2016-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho Kim ,  BiO Kim ,  Hyung Joon Kim ,  Young Seon Son ,  Su Jin Shin ,  Jae Young Ahn ,  Ju Mi Yun ,  HanMei Choi

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/7926

Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

公开(公告)号：US09716104B2

公开(公告)日：2017-07-25

申请号：US14987835

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  HanMei Choi

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11568

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/04

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US10468431B2

公开(公告)日：2019-11-05

申请号：US16027667

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho Kim ,  BiO Kim ,  Hyung Joon Kim ,  Young Seon Son ,  Su Jin Shin ,  Jae Young Ahn ,  Ju Mi Yun ,  HanMei Choi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/28 ,  H01L29/792

Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

公开(公告)号：US20190051554A1

公开(公告)日：2019-02-14

申请号：US15834676

申请日：2017-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Chul Song ,  Tae Gon Kim ,  Kyung In Choi ,  Sun Hong Choi ,  HanMei Choi ,  Sang Hoon Han

IPC: H01L21/687 ,  H01L21/265 ,  H01L21/67 ,  H01L21/02 ,  B23B31/02 ,  H01L21/683

Abstract: A wafer support assembly can include a wafer chuck including a first surface and a second surface, where the first surface can have a central region that is configured to hold a wafer during ion implantation into the wafer, and an edge region surrounding the central region beyond an edge of the wafer when held in the central region, and the second surface opposing the first surface. An edge mask structure can cover at least a portion of the edge region of the first surface, where the edge mask structure can have a mask body with an inclined side surface facing the central region.