公开(公告)号：US10553484B2

公开(公告)日：2020-02-04

申请号：US15959783

申请日：2018-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of active regions spaced apart from each other and extending linearly in parallel on a substrate. A gate electrode crosses the plurality of active regions, and respective drain regions are on and/or in respective ones of the active regions on a first side of the gate electrode and respective source regions are on and/or in respective ones of the active regions on a second side of the gate electrode. A drain plug is disposed on the drain regions and a source plug is disposed on the source regions. A gate plug is disposed on the gate electrode between the drain plug and the source plug such that a straight line passing through a center of the drain plug and a center of the source plug intersects the gate plug.

公开(公告)号：US20230207654A1

公开(公告)日：2023-06-29

申请号：US18054890

申请日：2022-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOO HYUN LEE ,  Heon Jong Shin ,  Hyun Ho Park ,  Seon-Bae Kim ,  Jin Young Park ,  Jae Ran Jang

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/285 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/161 ,  H01L29/401 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742

Abstract: A semiconductor device includes an active pattern that extends in a first direction; a plurality of gate structures that are spaced apart in the first direction, and include a gate electrode that extends in a second direction; a source/drain recess between adjacent gate structures; a source/drain pattern in the source/drain recess; a source/drain contact connected to the source/drain pattern and that includes a lower part on the source/drain pattern and an upper par; and a contact silicide film disposed along the lower part of the source/drain contact and between the source/drain contact and the source/drain region. The source/drain pattern includes a semiconductor liner film that extends along the source/drain recess and includes silicon germanium, a semiconductor filling film on the semiconductor liner film and that includes silicon germanium, and a semiconductor insertion film that extends along side walls of the lower part of the source/drain contact and includes silicon germanium.

公开(公告)号：US10340219B2

公开(公告)日：2019-07-02

申请号：US15868379

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki Hong ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L29/66 ,  H01L21/321 ,  H01L23/485 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/78 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

公开(公告)号：US20240128264A1

公开(公告)日：2024-04-18

申请号：US18331296

申请日：2023-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Min Yu ,  Heon Jong Shin ,  Doo Hyun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate, first and second active patterns extending in a first horizontal direction on the substrate, first and second gate electrodes extending in a second horizontal direction on the first and second active patterns, respectively, a first trench extending in the second horizontal direction between the first and second gate electrodes and separating the first and second active patterns, at least part of the first trench is in the substrate, an active cut extending along sidewalls and a bottom surface of the first trench and contacting each of the first and second active patterns, a second trench on the active cut in the first trench, and a flowable material layer in at least part of the second trench, the flowable material layer including a flowable insulating material and not being in contact with each of the substrate and the first and second active patterns.

公开(公告)号：US10818549B2

公开(公告)日：2020-10-27

申请号：US16724483

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/775

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US10658288B2

公开(公告)日：2020-05-19

申请号：US16420825

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki Hong ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/321 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/768 ,  H01L23/485 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction. A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

公开(公告)号：US20250056838A1

公开(公告)日：2025-02-13

申请号：US18584688

申请日：2024-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Woo Nam ,  Heon Jong Shin ,  Jae Ran Jang

IPC: H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device comprises a back insulating pattern comprising a first region, and a second region and extending in a first direction, a plurality of sheet patterns disposed on the back insulating pattern, and extending in the first direction, a first source/drain pattern disposed on the first region of the back insulating pattern, and connected to the plurality of sheet patterns, a second source/drain pattern disposed on the second region of the back insulating pattern, and connected to the plurality of sheet patterns, a gate electrode extending in a second direction crossing the first direction, and surrounding the plurality of sheet patterns, a first back source/drain contact that extends into the first region of the back insulating pattern, and connected to the first source/drain pattern and a second back source/drain contact that extends into the second region of the back insulating pattern, and connected to the second source/drain pattern.

公开(公告)号：US11778801B2

公开(公告)日：2023-10-03

申请号：US17185102

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hun Jung ,  Heon Jong Shin ,  Min Chan Gwak ,  Sung Moon Lee ,  Jeong Ki Hwang

IPC: H10B10/00 ,  H01L23/528 ,  H01L21/768

CPC classification number: H10B10/12 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/528 ,  H10B10/125

Abstract: A semiconductor device comprises a first gate structure extending in a first direction and including a first gate electrode and a first gate capping pattern, a second gate structure spaced apart from the first gate structure and extending in the first direction, and including a second gate electrode and a second gate capping pattern, an active pattern extending in a second direction, the active pattern below the second gate structure, an epitaxial pattern on one side of the second gate structure and on the active pattern, a gate contact connected to the first gate electrode, and a node contact connected to the second gate electrode and to the epitaxial pattern. An upper surface of the gate contact is at a same level as the first gate capping pattern, and an upper surface of the node contact is lower than the upper surface of the first gate capping pattern.

公开(公告)号：US11721581B2

公开(公告)日：2023-08-08

申请号：US17031279

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Chan Gwak ,  Hwi Chan Jun ,  Heon Jong Shin ,  So Ra You ,  Sang Hyun Lee ,  In Chan Hwang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L29/775

CPC classification number: H01L21/76897 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/456 ,  H01L29/775 ,  H01L29/785

Abstract: A semiconductor device includes active regions, a gate electrode, respective drain regions, respective source regions, a drain contact structure, a source contact structure, and a gate contact structure. The active regions extend linearly in parallel on a substrate. The gate electrode crosses the active regions. The drain regions are on and/or in the active regions on a first side of the gate electrode. The respective source regions are on and/or in the active regions on a second side of the gate electrode. The drain contact structure is on multiple drain regions. The source contact structure is on multiple source regions. The gate contact structure is on the gate electrode between the drain and source contact structures. The gate contact structure includes a gate plug and an upper gate plug directly on the gate plug. A center of the gate contact structure overlies only one of the active regions.

公开(公告)号：US20180358293A1

公开(公告)日：2018-12-13

申请号：US15868379

申请日：2018-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seul Ki HONG ,  Heon Jong Shin ,  Hwi Chan Jun ,  Min Chan Gwak

IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32115 ,  H01L21/32137 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53261 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction, A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.