公开(公告)号：US11600638B2

公开(公告)日：2023-03-07

申请号：US17136851

申请日：2020-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Lee ,  Sunggil Kim ,  Seulye Kim ,  Hwaeon Shin ,  Joonsuk Lee ,  Hyeeun Hong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/10 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L21/28

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.

公开(公告)号：US10930739B2

公开(公告)日：2021-02-23

申请号：US16186915

申请日：2018-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Dongkyum Kim ,  Sunggil Kim ,  Seulye Kim ,  Sangsoo Lee ,  Hyeeun Hong

IPC: H01L29/10 ,  H01L27/11556 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.

公开(公告)号：US11764268B2

公开(公告)日：2023-09-19

申请号：US17749719

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Kyengmun Kang ,  Juyon Suh ,  Hyeeun Hong

IPC: H01L29/10 ,  H01L25/07 ,  H01L23/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L29/1037 ,  H01L24/08 ,  H01L25/074 ,  H01L2224/08146 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.

公开(公告)号：US10903231B2

公开(公告)日：2021-01-26

申请号：US16217696

申请日：2018-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Lee ,  Sunggil Kim ,  Seulye Kim ,  Hwaeon Shin ,  Joonsuk Lee ,  Hyeeun Hong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/10 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L21/28

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method includes sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures that penetrate the mold structure, forming a trench that penetrates the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern that fills the horizontal recess region.

公开(公告)号：US11956967B2

公开(公告)日：2024-04-09

申请号：US17222403

申请日：2021-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Kyengmun Kang ,  Hyeeun Hong

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: An integrated circuit device includes a peripheral circuit structure arranged on a substrate, a gate stack arranged on the peripheral circuit structure and including a plurality of gate electrodes, and a dam structure formed in a dam opening portion that passes through the gate stack. The dam structure includes an insulation spacer on an inner wall of the dam opening portion and a pair of sloped sidewalls at an upper side of the dam opening portion, and a buried layer filling an inside of the dam opening portion and including an air space. The integrated circuit device further includes a mold gate stack surrounded by the dam structure and including a plurality of mold layers, a plurality of conductive lines arranged on the gate stack, and a plurality of through electrodes connected to the plurality of conductive lines, passing through the mold gate stack, and surrounded by the dam structure.

公开(公告)号：US11342415B2

公开(公告)日：2022-05-24

申请号：US17085467

申请日：2020-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Kyengmun Kang ,  Juyon Suh ,  Hyeeun Hong

IPC: H01L29/10 ,  H01L25/07 ,  H01L27/11 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion.