公开(公告)号：US08970014B2

公开(公告)日：2015-03-03

申请号：US14020021

申请日：2013-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin Lim ,  Hyung-Suk Jung ,  Yun-Ki Choi

IPC: H01L29/02

CPC classification number: H01L29/02 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28194 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517

Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.

Abstract translation: 提供半导体器件和形成半导体器件的方法，所述半导体器件包括在衬底上的第一介电层和第一介电层上的第二电介质层。 第一电介质层的碳浓度低于第二电介质层。

公开(公告)号：US10566433B2

公开(公告)日：2020-02-18

申请号：US16030291

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Hyuk Yim ,  Wan-Don Kim ,  Jong-Han Lee ,  Hyung-Suk Jung ,  Sang-Jin Hyun

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor formed in the first region and formed by a first gate line including a first lower metal-containing layer and a first upper metal-containing layer, and a second transistor formed in the second region and formed by a second gate line having an equal width to that of the first gate line and including a second lower metal-containing layer and a second upper metal-containing layer on the second upper metal-containing layer, wherein each of an uppermost end of the first upper metal-containing layer and an uppermost end of the second lower metal-containing layer has a higher level than an uppermost end of the first lower metal-containing layer.

公开(公告)号：US09218977B2

公开(公告)日：2015-12-22

申请号：US14015414

申请日：2013-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jun Won ,  Weon-Hong Kim ,  Moon-Kyun Song ,  Hyung-Suk Jung

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L21/28185 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/1104 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A fabricating method of a semiconductor device includes stacking a high-k dielectric film not containing silicon (Si) and an insulating film containing silicon (Si) on a substrate, and diffusing Si contained in the insulating film into the high-k dielectric film by annealing the substrate having the high-k dielectric film and the insulating film stacked thereon.

Abstract translation: 半导体器件的制造方法包括在基板上堆叠不含硅（Si）的高k电介质膜和含硅（Si）的绝缘膜，并且将包含在绝缘膜中的Si扩散到高k电介质膜中，由 退火具有高k电介质膜的基板和堆叠在其上的绝缘膜。

公开(公告)号：US20150162201A1

公开(公告)日：2015-06-11

申请号：US14477273

申请日：2014-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-Hee Lee ,  Min-Woo Song ,  Seok-Jun Won ,  Hyung-Suk Jung

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/28247 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate electrode and a gate mask sequentially stacked on a substrate is formed. A spacer is formed on a sidewall of the dummy gate structure. The gate mask is formed to expose the dummy gate electrode and to form a recess on the spacer. A capping layer pattern is formed to fill the recess in the spacer. The exposed dummy gate electrode is replaced with a gate electrode.

Abstract translation: 在制造半导体器件的方法中，形成包括依次层叠在基板上的伪栅极电极和栅极掩模的虚拟栅极结构。 在虚拟栅极结构的侧壁上形成间隔物。 形成栅极掩模以暴露伪栅电极并在间隔物上形成凹陷。 形成覆盖层图案以填充间隔件中的凹部。 暴露的虚拟栅电极被栅电极代替。

公开(公告)号：US09035398B2

公开(公告)日：2015-05-19

申请号：US14010961

申请日：2013-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Jun Won ,  Suk-Hoon Kim ,  Hyung-Suk Jung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including a trench, a gate insulating film in the trench, a diffusion film on the gate insulating film, the diffusion film including a first diffusion material, a gate metal structure on the diffusion film, the gate metal structure including a second diffusion material, and a diffusion prevention film between the gate metal structure and the diffusion film, the diffusion prevention film being configured to prevent diffusion of the second diffusion material from the gate metal structure, the first diffusion material diffused from the diffusion film exists in the gate insulating film.

Abstract translation: 一种半导体器件，包括：衬底上的层间绝缘膜，所述层间绝缘膜包括沟槽，所述沟槽中的栅极绝缘膜，所述栅极绝缘膜上的扩散膜，所述扩散膜包括第一扩散材料，栅极金属结构 在扩散膜上，包括第二扩散材料的栅极金属结构和栅极金属结构和扩散膜之间的扩散防止膜，所述扩散防止膜被配置为防止第二扩散材料从栅极金属结构扩散， 从扩散膜扩散的第一扩散材料存在于栅极绝缘膜中。

公开(公告)号：US09034714B2

公开(公告)日：2015-05-19

申请号：US14011095

申请日：2013-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Jun Won ,  Hyung-Suk Jung

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device includes providing a dummy gate insulation film formed on a substrate, the dummy gate insulation film including a first material and providing a spacer formed at least one side of the gate insulation film, the spacer including the first material, removing the first material included in the dummy gate insulation film by a first process, removing the dummy gate insulation film from which the first material has been removed by a second process different from the first process, and sequentially forming a gate insulation film and a gate electrode structure on the substrate.

Abstract translation: 一种制造半导体器件的方法包括：提供形成在衬底上的虚拟栅极绝缘膜，所述虚拟栅极绝缘膜包括第一材料并提供形成在所述栅极绝缘膜的至少一个侧面上的间隔物，所述间隔物包括所述第一材料， 通过第一工序除去包含在虚拟栅极绝缘膜中的第一材料，通过与第一工艺不同的第二工序除去已经除去第一材料的虚拟栅极绝缘膜，并顺序地形成栅极绝缘膜和栅极 基板上的电极结构。