公开(公告)号：US20180145252A1

公开(公告)日：2018-05-24

申请号：US15862926

申请日：2018-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HYUN JEONG ,  JIN-WOO LEE ,  GWAN-HYEOB KOH ,  DAE-HWAN KANG

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/144 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

公开(公告)号：US20200152869A1

公开(公告)日：2020-05-14

申请号：US16743594

申请日：2020-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-HYUN JEONG ,  JIN-WOO LEE ,  GWAN-HYEOB KOH ,  DAE-HWAN KANG

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.

公开(公告)号：US20190140022A1

公开(公告)日：2019-05-09

申请号：US16135315

申请日：2018-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JI-HYUN JEONG ,  Dae-Hwan Kang ,  Du-Eung Kim ,  Kwang-Jin Lee

IPC: H01L27/24 ,  G11C5/06 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00 ,  H01L27/22

Abstract: A memory device includes a first word line extending in a first direction on a substrate, a first bit line extending in a second direction on the first word line, a first memory cell disposed between the first word line and the first bit line, a second word line extending in the first direction on the first bit line, a second bit line extending in the second direction on the second word line, a second memory cell disposed between the second word line and the second bit line, and a first bit line connection structure connected to the first bit line and the second bit line. The first bit line connection structure includes a first bit line contact connected to the first bit line and a second bit line contact, which is connected to the second bit line and vertically overlaps the first bit line contact.