公开(公告)号：US09899323B2

公开(公告)日：2018-02-20

申请号：US15377723

申请日：2016-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jun Seong ,  Jae-hwang Sim

IPC: H01L21/28 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/5283 ,  H01L24/09

Abstract: An integrated circuit device includes a first conductive line and a second conductive line that are spaced apart from each other and extend in a first direction to be parallel to each other; and a contact pad including a pad body including a first branch portion from which the first conductive line branches and a second branch portion from which the second conductive line branches and a loop branch portion that is located between the first branch portion and the second branch portion and protrudes from the pad body. Related devices and fabrication methods are also discussed.

公开(公告)号：US20170309568A1

公开(公告)日：2017-10-26

申请号：US15377723

申请日：2016-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-jun Seong ,  Jae-hwang Sim

IPC: H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L24/09

Abstract: An integrated circuit device includes a first conductive line and a second conductive line that are spaced apart from each other and extend in a first direction to be parallel to each other; and a contact pad including a pad body including a first branch portion from which the first conductive line branches and a second branch portion from which the second conductive line branches and a loop branch portion that is located between the first branch portion and the second branch portion and protrudes from the pad body. Related devices and fabrication methods are also discussed.

公开(公告)号：US20150348795A1

公开(公告)日：2015-12-03

申请号：US14568764

申请日：2014-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-sung Song ,  Jin-hyun Shin ,  Jae-hwang Sim ,  Joon-sung Lim ,  Bong-hyun Choi

IPC: H01L21/308 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/76224 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.

Abstract translation: 在使用三重图案化工艺的半导体器件的制造方法中，在要蚀刻的层上形成覆盖侧壁的多孔层和含聚合物的图案的上表面。 通过多孔层将分解气体供给到含聚合物的图案，并且含有聚合物的图案的一部分被分解以形成还原的含聚合物的图案，并且在含还原聚合物的图案和多孔层之间形成空隙 。 去除多孔层的一部分以形成与含还原聚合物的图案间隔开的多孔间隔物图案。 通过使用还原的含聚合物图案和多孔间隔物图案作为蚀刻掩模来蚀刻待蚀刻的层。

公开(公告)号：US09330931B2

公开(公告)日：2016-05-03

申请号：US14568764

申请日：2014-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-sung Song ,  Jin-hyun Shin ,  Jae-hwang Sim ,  Joon-sung Lim ,  Bong-hyun Choi

IPC: H01L21/308 ,  H01L21/768 ,  H01L21/033

CPC classification number: H01L21/3086 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/76224 ,  H01L21/768

Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.

Abstract translation: 在使用三重图案化工艺的半导体器件的制造方法中，在要蚀刻的层上形成覆盖侧壁的多孔层和含聚合物的图案的上表面。 通过多孔层将分解气体供给到含聚合物的图案，并且含有聚合物的图案的一部分被分解以形成还原的含聚合物的图案，并且在含还原聚合物的图案和多孔层之间形成空隙 。 去除多孔层的一部分以形成与含还原聚合物的图案间隔开的多孔间隔物图案。 通过使用还原的含聚合物图案和多孔间隔物图案作为蚀刻掩模来蚀刻待蚀刻的层。

公开(公告)号：US08629052B2

公开(公告)日：2014-01-14

申请号：US13652550

申请日：2012-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

IPC: H01L21/28 ,  H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.

Abstract translation: 提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。 半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到 第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。