公开(公告)号：US10651179B2

公开(公告)日：2020-05-12

申请号：US15992623

申请日：2018-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US09508644B2

公开(公告)日：2016-11-29

申请号：US14929737

申请日：2015-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-kwon Kim ,  Ki-il Kim ,  Ah-young Cheon ,  Myeong-cheol Kim ,  Yong-jin Kim

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213 ,  H01L23/48

CPC classification number: H01L23/5283 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/32139 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.

公开(公告)号：US10014304B2

公开(公告)日：2018-07-03

申请号：US15333491

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-bae Park ,  Ja-hum Ku ,  Myeong-cheol Kim ,  Jin-wook Lee ,  Sung-kee Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8238 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

公开(公告)号：US08987836B2

公开(公告)日：2015-03-24

申请号：US13780855

申请日：2013-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-cheol Kim ,  Cheol Kim ,  Jaehun Seo ,  YooJung Lee ,  Kisoo Chang ,  Siyoung Choi

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/7851

Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

Abstract translation: 场效应晶体管，其包括基板上的源极区域和漏极区域，从基板的顶面突出的翅片基板，从翅片基部向上延伸并将源极区域与漏极区域连接的多个翅片部， 翅片部分上的电极，以及翅片部分和栅电极之间的栅极电介质。 基板的顶面可以包括多个凹槽（例如，多个凸部和多个凹部）。 此外，可以设置器件隔离层以暴露多个翅片部分的上部并覆盖多个凹槽的顶表面。

公开(公告)号：US08629052B2

公开(公告)日：2014-01-14

申请号：US13652550

申请日：2012-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

IPC: H01L21/28 ,  H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.

Abstract translation: 提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。 半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到 第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。

公开(公告)号：USRE49375E1

公开(公告)日：2023-01-17

申请号：US17129109

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-cheol Kim ,  Cheol Kim ,  Jaehun Seo ,  YooJung Lee ,  Kisoo Chang ,  Siyoung Choi

IPC: H01L29/78 ,  H01L29/66

Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

公开(公告)号：US10304840B2

公开(公告)日：2019-05-28

申请号：US15084785

申请日：2016-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-hee Bai ,  Myeong-cheol Kim ,  Kwan-heum Lee ,  Do-hyoung Kim ,  Jin-wook Lee ,  Seung-mo Ha ,  Dong-Hoon Khang

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.